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// PART OF THIS FILE AT ALL TIMES.
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// PART OF THIS FILE AT ALL TIMES.
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//
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//
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// Project : Series-7 Integrated Block for PCI Express
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// Project : Series-7 Integrated Block for PCI Express
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// File : cl_a7pcie_x4_qpll_drp.v
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// File : cl_a7pcie_x4_qpll_drp.v
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// Version : 1.9
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// Version : 1.10
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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// Filename : qpll_drp.v
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// Filename : qpll_drp.v
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// Description : QPLL DRP Module for 7 Series Transceiver
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// Description : QPLL DRP Module for 7 Series Transceiver
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// Version : 18.2
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// Version : 18.2
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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output [ 8:0] DRP_FSM
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output [ 8:0] DRP_FSM
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);
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);
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//---------- Input Registers ---------------------------
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//---------- Input Registers ---------------------------
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reg ovrd_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg ovrd_reg1;
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reg gen3_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gen3_reg1;
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reg qplllock_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg qplllock_reg1;
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reg start_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg start_reg1;
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reg [15:0] do_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [15:0] do_reg1;
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reg rdy_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rdy_reg1;
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reg ovrd_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg ovrd_reg2;
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reg gen3_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gen3_reg2;
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reg qplllock_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg qplllock_reg2;
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reg start_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg start_reg2;
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reg [15:0] do_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [15:0] do_reg2;
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reg rdy_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rdy_reg2;
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//---------- Internal Signals --------------------------
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//---------- Internal Signals --------------------------
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reg [ 1:0] load_cnt = 2'd0;
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reg [ 1:0] load_cnt = 2'd0;
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reg [ 2:0] index = 3'd0;
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reg [ 2:0] index = 3'd0;
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reg mode = 1'd0;
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reg mode = 1'd0;
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