URL https://opencores.org/ocsvn/pcie_ds_dma/pcie_ds_dma/trunk

Subversion Repositories pcie_ds_dma

[/] [pcie_ds_dma/] [trunk/] [projects/] [sp605_lx45t_wishbone/] [compile.cfg] - Diff between revs 51 and 53

Rev 51	Rev 53
Line 705...	Line 705...
`Enabled=1`	`Enabled=1`
`[file:.\src\DESIGN_STATUS\2013_08_02_00_11\synthesis_synthesis.dfml]`	`[file:.\src\DESIGN_STATUS\2013_08_02_00_11\synthesis_synthesis.dfml]`
`Enabled=1`	`Enabled=1`
`[file:.\src\DESIGN_STATUS\2013_08_02_00_11\implement_ver1_rev1_implementation.dfml]`	`[file:.\src\DESIGN_STATUS\2013_08_02_00_11\implement_ver1_rev1_implementation.dfml]`
`Enabled=1`	`Enabled=1`
	`[file:.\src\pcie_src\components\coregen_s6\ctrl_fifo512x64st_v0.ngc]`
	`Enabled=1`
	`[file:.\src\pcie_src\components\coregen_s6\ctrl_fifo512x64st_v0.vhd]`
	`Enabled=1`
	`[file:.\src\pcie_src\components\coregen_s6\ctrl_fifo512x64st_v0.xco]`
	`Enabled=1`
	`[file:.\src\pcie_src\components\coregen_s6\ctrl_fifo64x34fw.ngc]`
	`Enabled=1`
	`[file:.\src\pcie_src\components\coregen_s6\ctrl_fifo64x34fw.vhd]`
	`Enabled=1`
	`[file:.\src\pcie_src\components\coregen_s6\ctrl_fifo64x34fw.xco]`
	`Enabled=1`
	`[file:.\src\pcie_src\components\coregen_s6\ctrl_fifo64x37st.ngc]`
	`Enabled=1`
	`[file:.\src\pcie_src\components\coregen_s6\ctrl_fifo64x37st.vhd]`
	`Enabled=1`
	`[file:.\src\pcie_src\components\coregen_s6\ctrl_fifo64x37st.xco]`
	`Enabled=1`