| Line 144... |
Line 144... |
[DefineMacro]
|
[DefineMacro]
|
Global=
|
Global=
|
|
|
[Folders]
|
[Folders]
|
Name3=Makefiles
|
Name3=Makefiles
|
Directory3=e:\prog\pcie_ds_dma\trunk\projects\sp605_lx45t_wishbone\
|
Directory3=E:\prog\pcie_ds_dma\trunk\projects\sp605_lx45t_wishbone\
|
Extension3=mak
|
Extension3=mak
|
Name4=Memory
|
Name4=Memory
|
Directory4=e:\prog\pcie_ds_dma\trunk\projects\sp605_lx45t_wishbone\src
|
Directory4=E:\prog\pcie_ds_dma\trunk\projects\sp605_lx45t_wishbone\src
|
Extension4=mem;mif;hex
|
Extension4=mem;mif;hex
|
Name5=Dll Libraries
|
Name5=Dll Libraries
|
Directory5=e:\prog\pcie_ds_dma\trunk\projects\sp605_lx45t_wishbone\
|
Directory5=E:\prog\pcie_ds_dma\trunk\projects\sp605_lx45t_wishbone\
|
Extension5=dll
|
Extension5=dll
|
Name6=PDF
|
Name6=PDF
|
Directory6=e:\prog\pcie_ds_dma\trunk\projects\sp605_lx45t_wishbone\
|
Directory6=E:\prog\pcie_ds_dma\trunk\projects\sp605_lx45t_wishbone\
|
Extension6=pdf
|
Extension6=pdf
|
Name7=HTML
|
Name7=HTML
|
Directory7=e:\prog\pcie_ds_dma\trunk\projects\sp605_lx45t_wishbone\
|
Directory7=E:\prog\pcie_ds_dma\trunk\projects\sp605_lx45t_wishbone\
|
Extension7=
|
Extension7=
|
|
|
[Groups]
|
|
pcie_src=1
|
|
pcie_src\components=1
|
|
pcie_src\components\block_main=1
|
|
pcie_src\components\coregen=1
|
|
pcie_src\components\pcie_core=1
|
|
pcie_src\components\rtl=1
|
|
pcie_src\pcie_core64_m1=1
|
|
pcie_src\pcie_core64_m1\pcie_ctrl=1
|
|
pcie_src\pcie_core64_m1\pcie_fifo_ext=1
|
|
pcie_src\pcie_core64_m1\source=0
|
|
pcie_src\pcie_core64_m1\source_s6=1
|
|
pcie_src\pcie_core64_m1\source_virtex6=1
|
|
pcie_src\pcie_core64_m1\top=1
|
|
pcie_src\pcie_sim=1
|
|
pcie_src\pcie_sim\dsport=1
|
|
pcie_src\pcie_sim\sim=1
|
|
testbench=1
|
|
testbench\modelsim=1
|
|
testbench\modelsim\zz_do=1
|
|
testbench\modelsim\required_tests=1
|
|
testbench\modelsim\required_tests\test0=1
|
|
testbench\modelsim\required_tests\test0\zz_do=1
|
|
testbench\ahdl=1
|
|
top=1
|
|
wishbone=1
|
|
wishbone\block_test_check=1
|
|
wishbone\block_test_generate=1
|
|
wishbone\cross=1
|
|
wishbone\doc=1
|
|
wishbone\coregen=1
|
|
wishbone\testbecnh=1
|
|
wishbone\testbecnh\dev_pb_wishbone_ctrl=1
|
|
wishbone\testbecnh\dev_pb_wishbone_ctrl\sim=1
|
|
wishbone\testbecnh\dev_pb_wishbone_ctrl\sim\zz_do=1
|
|
wishbone\testbecnh\dev_test_check=1
|
|
wishbone\testbecnh\dev_test_check\sim=1
|
|
wishbone\testbecnh\dev_test_check\sim\zz_do=1
|
|
wishbone\testbecnh\dev_test_gen=1
|
|
wishbone\testbecnh\dev_test_gen\sim=1
|
|
wishbone\testbecnh\dev_test_gen\sim\zz_do=1
|
|
wishbone\testbecnh\dev_wb_cross=1
|
|
wishbone\testbecnh\dev_wb_cross\sim=1
|
|
wishbone\testbecnh\dev_wb_cross\sim\zz_do=1
|
|
testbench\log=1
|
|
post-synthesis=1
|
|
DESIGN_STATUS=1
|
|
DESIGN_STATUS\2013_07_26_01_18=1
|
|
|
|
[Verilog Library]
|
[Verilog Library]
|
ovi_unimacro=
|
ovi_unimacro=
|
ovi_unisim=
|
ovi_unisim=
|
ovi_xilinxcorelib=
|
ovi_xilinxcorelib=
|
|
|
| Line 303... |
Line 254... |
MOVE_LAST_FF_STAGE=1
|
MOVE_LAST_FF_STAGE=1
|
JOB_DESCRIPTION=SynthesisTask
|
JOB_DESCRIPTION=SynthesisTask
|
SERVERFARM_INCLUDE_INPUT_FILES=*.*
|
SERVERFARM_INCLUDE_INPUT_FILES=*.*
|
SERVERFARM_EXCLUDE_INPUT_FILES=log*.*:implement*.*
|
SERVERFARM_EXCLUDE_INPUT_FILES=log*.*:implement*.*
|
JOB_SFM_RESOURCE=
|
JOB_SFM_RESOURCE=
|
LAST_RUN=1374786428
|
LAST_RUN=1375386863
|
OUTPUT_NETLIST=synthesis\sp605_lx45t_wishbone.ngc
|
OUTPUT_NETLIST=synthesis\sp605_lx45t_wishbone.ngc
|
OUTPUT_SIMUL_NETLIST=synthesis\sp605_lx45t_wishbone.vhd
|
OUTPUT_SIMUL_NETLIST=synthesis\sp605_lx45t_wishbone.vhd
|
|
|
[PHYS_SYNTHESIS]
|
[PHYS_SYNTHESIS]
|
FAMILY=Xilinx13x SPARTAN6
|
FAMILY=Xilinx13x SPARTAN6
|
| Line 338... |
Line 289... |
JOB_DESCRIPTION=ImplementationTask
|
JOB_DESCRIPTION=ImplementationTask
|
SERVERFARM_INCLUDE_INPUT_FILES=*.*
|
SERVERFARM_INCLUDE_INPUT_FILES=*.*
|
SERVERFARM_EXCLUDE_INPUT_FILES=log\*.*
|
SERVERFARM_EXCLUDE_INPUT_FILES=log\*.*
|
JOB_SFM_RESOURCE=
|
JOB_SFM_RESOURCE=
|
SYNTH_TOOL_RESET=0
|
SYNTH_TOOL_RESET=0
|
LAST_RUN=1374786709
|
LAST_RUN=1375387391
|
|
|
[IMPLEMENTATION_XILINX13]
|
[IMPLEMENTATION_XILINX13]
|
impl_opt(dont_run_translate)=0
|
impl_opt(dont_run_translate)=0
|
impl_opt(dont_run_map)=0
|
impl_opt(dont_run_map)=0
|
impl_opt(dont_run_place)=0
|
impl_opt(dont_run_place)=0
|
| Line 351... |
Line 302... |
impl_opt(dont_run_fit)=0
|
impl_opt(dont_run_fit)=0
|
impl_opt(dont_run_bitgen)=0
|
impl_opt(dont_run_bitgen)=0
|
Macro_Search_Path={src\wishbone\coregen} {src\pcie_src\components\coregen}
|
Macro_Search_Path={src\wishbone\coregen} {src\pcie_src\components\coregen}
|
impl_opt(partitions_file)=
|
impl_opt(partitions_file)=
|
impl_opt(use_partitions_file)=0
|
impl_opt(use_partitions_file)=0
|
impl_opt(smart_guide_file)=
|
impl_opt(smart_guide_file)=implement\ver1\rev1\sp605_lx45t_wishbone_guide.ncd
|
impl_opt(use_smart_guide)=0
|
impl_opt(use_smart_guide)=0
|
impl_opt(edif_str)=synthesis\sp605_lx45t_wishbone.ngc
|
impl_opt(edif_str)=synthesis\sp605_lx45t_wishbone.ngc
|
impl_opt(_family_sel)=Xilinx13x SPARTAN6
|
impl_opt(_family_sel)=Xilinx13x SPARTAN6
|
impl_opt(_device_sel)=6slx45tfgg484
|
impl_opt(_device_sel)=6slx45tfgg484
|
impl_opt(_speed_sel)=-3
|
impl_opt(_speed_sel)=-3
|
impl_opt(Effort_Level)=Standard
|
impl_opt(Effort_Level)=High
|
impl_opt(netlist_format)=1
|
impl_opt(netlist_format)=1
|
impl_opt(auto_close)=0
|
impl_opt(auto_close)=0
|
impl_opt(override_existing_project)=1
|
impl_opt(override_existing_project)=1
|
impl_opt(bat_file_name)=
|
impl_opt(bat_file_name)=
|
impl_opt(is_bat_mode)=0
|
impl_opt(is_bat_mode)=0
|
| Line 401... |
Line 352... |
impl_opt(Map_Effort_Level)=High
|
impl_opt(Map_Effort_Level)=High
|
impl_opt(Allow_Logic_Opt_Across_Hier)=1
|
impl_opt(Allow_Logic_Opt_Across_Hier)=1
|
impl_opt(Use_Rloc_Constraints)=Yes
|
impl_opt(Use_Rloc_Constraints)=Yes
|
impl_opt(Show_Map_Slice_Logic_Into_Unused_Blocks)=0
|
impl_opt(Show_Map_Slice_Logic_Into_Unused_Blocks)=0
|
impl_opt(Other_Map_Options)=
|
impl_opt(Other_Map_Options)=
|
impl_opt(Extra_Effort)=None
|
impl_opt(Extra_Effort)=Normal
|
impl_opt(Retain_Hiearchy)=1
|
impl_opt(Retain_Hiearchy)=1
|
impl_opt(Change_Device_Speed)=3
|
impl_opt(Change_Device_Speed)=3
|
impl_opt(Tristate_Configuration_Pulsee)=0
|
impl_opt(Tristate_Configuration_Pulsee)=0
|
impl_opt(Reset_Configuration_Pulsee)=100
|
impl_opt(Reset_Configuration_Pulsee)=100
|
impl_opt(Generate_Architecture_Only)=0
|
impl_opt(Generate_Architecture_Only)=0
|
| Line 418... |
Line 369... |
impl_opt(Insert_ChipScope_Core)=0
|
impl_opt(Insert_ChipScope_Core)=0
|
impl_opt(Run_ChipScope_Core_Inserter_GUI)=1
|
impl_opt(Run_ChipScope_Core_Inserter_GUI)=1
|
impl_opt(ChipScope_Core_Inserter_Project_File)=synthesis\sp605_lx45t_wishbone.cdc
|
impl_opt(ChipScope_Core_Inserter_Project_File)=synthesis\sp605_lx45t_wishbone.cdc
|
impl_opt(_use_filter_messages)=0
|
impl_opt(_use_filter_messages)=0
|
impl_opt(_filter_messages)=
|
impl_opt(_filter_messages)=
|
impl_opt(AdvMap_Extra_Effort)=None
|
impl_opt(AdvMap_Extra_Effort)=Normal
|
impl_opt(Map_Starting_Placer_Cost_Table)=1
|
impl_opt(Map_Starting_Placer_Cost_Table)=1
|
impl_opt(Show_Register_Duplication)=0
|
impl_opt(Show_Register_Duplication)=0
|
impl_opt(Include_Function_In_Verilog_File)=1
|
impl_opt(Include_Function_In_Verilog_File)=1
|
impl_opt(Include_Simprim_Models_In_Verilog_File)=0
|
impl_opt(Include_Simprim_Models_In_Verilog_File)=0
|
impl_opt(Show_Equivalent_Register_Removal)=1
|
impl_opt(Show_Equivalent_Register_Removal)=1
|
| Line 536... |
Line 487... |
impl_opt(Register_Ordering)=4
|
impl_opt(Register_Ordering)=4
|
|
|
[PCB_INTERFACE]
|
[PCB_INTERFACE]
|
FAMILY=
|
FAMILY=
|
|
|
|
[Groups]
|
|
pcie_src=1
|
|
pcie_src\components=1
|
|
pcie_src\components\block_main=1
|
|
pcie_src\components\coregen=1
|
|
pcie_src\components\pcie_core=1
|
|
pcie_src\components\rtl=1
|
|
pcie_src\pcie_core64_m1=1
|
|
pcie_src\pcie_core64_m1\pcie_ctrl=1
|
|
pcie_src\pcie_core64_m1\pcie_fifo_ext=1
|
|
pcie_src\pcie_core64_m1\source=0
|
|
pcie_src\pcie_core64_m1\source_s6=1
|
|
pcie_src\pcie_core64_m1\source_virtex6=1
|
|
pcie_src\pcie_core64_m1\top=1
|
|
pcie_src\pcie_sim=1
|
|
pcie_src\pcie_sim\dsport=1
|
|
pcie_src\pcie_sim\sim=1
|
|
testbench=1
|
|
testbench\modelsim=1
|
|
testbench\modelsim\zz_do=1
|
|
testbench\modelsim\required_tests=1
|
|
testbench\modelsim\required_tests\test0=1
|
|
testbench\modelsim\required_tests\test0\zz_do=1
|
|
testbench\ahdl=1
|
|
testbench\log=1
|
|
top=1
|
|
wishbone=1
|
|
wishbone\block_test_check=1
|
|
wishbone\block_test_generate=1
|
|
wishbone\cross=1
|
|
wishbone\doc=1
|
|
wishbone\coregen=1
|
|
wishbone\testbecnh=1
|
|
wishbone\testbecnh\dev_pb_wishbone_ctrl=1
|
|
wishbone\testbecnh\dev_pb_wishbone_ctrl\sim=1
|
|
wishbone\testbecnh\dev_pb_wishbone_ctrl\sim\zz_do=1
|
|
wishbone\testbecnh\dev_test_check=1
|
|
wishbone\testbecnh\dev_test_check\sim=1
|
|
wishbone\testbecnh\dev_test_check\sim\zz_do=1
|
|
wishbone\testbecnh\dev_test_gen=1
|
|
wishbone\testbecnh\dev_test_gen\sim=1
|
|
wishbone\testbecnh\dev_test_gen\sim\zz_do=1
|
|
wishbone\testbecnh\dev_wb_cross=1
|
|
wishbone\testbecnh\dev_wb_cross\sim=1
|
|
wishbone\testbecnh\dev_wb_cross\sim\zz_do=1
|
|
post-synthesis=1
|
|
DESIGN_STATUS=1
|
|
DESIGN_STATUS\2013_07_26_01_18=1
|
|
DESIGN_STATUS\2013_08_02_00_11=1
|
|
|
[Files]
|
[Files]
|
pcie_src\components\block_main/block_pe_main.vhd=-1
|
pcie_src\components\block_main/block_pe_main.vhd=-1
|
pcie_src\components\coregen/ctrl_fifo64x34fw.ngc=-1
|
pcie_src\components\coregen/ctrl_fifo64x34fw.ngc=-1
|
pcie_src\components\coregen/ctrl_fifo64x34fw.vhd=-1
|
pcie_src\components\coregen/ctrl_fifo64x34fw.vhd=-1
|
pcie_src\components\coregen/ctrl_fifo64x34fw.xco=-1
|
pcie_src\components\coregen/ctrl_fifo64x34fw.xco=-1
|
| Line 705... |
Line 706... |
testbench\log/console_test_read_4kB.log=-1
|
testbench\log/console_test_read_4kB.log=-1
|
testbench\log/file_id_0.log=-1
|
testbench\log/file_id_0.log=-1
|
testbench\log/file_id_1.log=-1
|
testbench\log/file_id_1.log=-1
|
testbench\log/file_id_2.log=-1
|
testbench\log/file_id_2.log=-1
|
testbench\log/global_tc_summary.log=-1
|
testbench\log/global_tc_summary.log=-1
|
|
testbench\log/console_test_read_reg.log=-1
|
|
testbench\log/file_id_3.log=-1
|
top/sp605_lx45t_wishbone.ucf=-1
|
top/sp605_lx45t_wishbone.ucf=-1
|
top/sp605_lx45t_wishbone_sopc_wb.vhd=-1
|
top/sp605_lx45t_wishbone_sopc_wb.vhd=-1
|
top/sp605_lx45t_wishbone.vhd=-1
|
top/sp605_lx45t_wishbone.vhd=-1
|
wishbone\block_test_check/block_check_wb_pkg.vhd=-1
|
wishbone\block_test_check/block_check_wb_pkg.vhd=-1
|
wishbone\block_test_check/block_check_wb_burst_slave.v=-1
|
wishbone\block_test_check/block_check_wb_burst_slave.v=-1
|
| Line 780... |
Line 783... |
DESIGN_STATUS\2013_07_26_01_18/DesignInformation.txt=-1
|
DESIGN_STATUS\2013_07_26_01_18/DesignInformation.txt=-1
|
DESIGN_STATUS\2013_07_26_01_18/DesignFiles.txt=-1
|
DESIGN_STATUS\2013_07_26_01_18/DesignFiles.txt=-1
|
DESIGN_STATUS\2013_07_26_01_18/LibrariesList.txt=-1
|
DESIGN_STATUS\2013_07_26_01_18/LibrariesList.txt=-1
|
DESIGN_STATUS\2013_07_26_01_18/synthesis_synthesis.dfml=-1
|
DESIGN_STATUS\2013_07_26_01_18/synthesis_synthesis.dfml=-1
|
DESIGN_STATUS\2013_07_26_01_18/implement_ver1_rev1_implementation.dfml=-1
|
DESIGN_STATUS\2013_07_26_01_18/implement_ver1_rev1_implementation.dfml=-1
|
|
DESIGN_STATUS\2013_08_02_00_11/ComputerInformation.txt=-1
|
|
DESIGN_STATUS\2013_08_02_00_11/DesignInformation.txt=-1
|
|
DESIGN_STATUS\2013_08_02_00_11/DesignFiles.txt=-1
|
|
DESIGN_STATUS\2013_08_02_00_11/LibrariesList.txt=-1
|
|
DESIGN_STATUS\2013_08_02_00_11/synthesis_synthesis.dfml=-1
|
|
DESIGN_STATUS\2013_08_02_00_11/implement_ver1_rev1_implementation.dfml=-1
|
|
|
[Files.Data]
|
[Files.Data]
|
.\src\pcie_src\components\block_main\block_pe_main.vhd=VHDL Source Code
|
.\src\pcie_src\components\block_main\block_pe_main.vhd=VHDL Source Code
|
.\src\pcie_src\components\coregen\ctrl_fifo64x34fw.ngc=External File
|
.\src\pcie_src\components\coregen\ctrl_fifo64x34fw.ngc=External File
|
.\src\pcie_src\components\coregen\ctrl_fifo64x34fw.vhd=VHDL Source Code
|
.\src\pcie_src\components\coregen\ctrl_fifo64x34fw.vhd=VHDL Source Code
|
| Line 950... |
Line 959... |
.\src\testbench\log\console_test_read_4kB.log=Text File
|
.\src\testbench\log\console_test_read_4kB.log=Text File
|
.\src\testbench\log\file_id_0.log=Text File
|
.\src\testbench\log\file_id_0.log=Text File
|
.\src\testbench\log\file_id_1.log=Text File
|
.\src\testbench\log\file_id_1.log=Text File
|
.\src\testbench\log\file_id_2.log=Text File
|
.\src\testbench\log\file_id_2.log=Text File
|
.\src\testbench\log\global_tc_summary.log=Text File
|
.\src\testbench\log\global_tc_summary.log=Text File
|
|
.\src\testbench\log\console_test_read_reg.log=Text File
|
|
.\src\testbench\log\file_id_3.log=Text File
|
.\src\top\sp605_lx45t_wishbone.ucf=External File
|
.\src\top\sp605_lx45t_wishbone.ucf=External File
|
.\src\top\sp605_lx45t_wishbone_sopc_wb.vhd=VHDL Source Code
|
.\src\top\sp605_lx45t_wishbone_sopc_wb.vhd=VHDL Source Code
|
.\src\top\sp605_lx45t_wishbone.vhd=VHDL Source Code
|
.\src\top\sp605_lx45t_wishbone.vhd=VHDL Source Code
|
.\src\wishbone\block_test_check\block_check_wb_pkg.vhd=VHDL Source Code
|
.\src\wishbone\block_test_check\block_check_wb_pkg.vhd=VHDL Source Code
|
.\src\wishbone\block_test_check\block_check_wb_burst_slave.v=Verilog Source Code
|
.\src\wishbone\block_test_check\block_check_wb_burst_slave.v=Verilog Source Code
|
| Line 1025... |
Line 1036... |
.\src\DESIGN_STATUS\2013_07_26_01_18\DesignInformation.txt=Text File
|
.\src\DESIGN_STATUS\2013_07_26_01_18\DesignInformation.txt=Text File
|
.\src\DESIGN_STATUS\2013_07_26_01_18\DesignFiles.txt=Text File
|
.\src\DESIGN_STATUS\2013_07_26_01_18\DesignFiles.txt=Text File
|
.\src\DESIGN_STATUS\2013_07_26_01_18\LibrariesList.txt=Text File
|
.\src\DESIGN_STATUS\2013_07_26_01_18\LibrariesList.txt=Text File
|
.\src\DESIGN_STATUS\2013_07_26_01_18\synthesis_synthesis.dfml=Text File
|
.\src\DESIGN_STATUS\2013_07_26_01_18\synthesis_synthesis.dfml=Text File
|
.\src\DESIGN_STATUS\2013_07_26_01_18\implement_ver1_rev1_implementation.dfml=Text File
|
.\src\DESIGN_STATUS\2013_07_26_01_18\implement_ver1_rev1_implementation.dfml=Text File
|
|
.\src\DESIGN_STATUS\2013_08_02_00_11\ComputerInformation.txt=Text File
|
|
.\src\DESIGN_STATUS\2013_08_02_00_11\DesignInformation.txt=Text File
|
|
.\src\DESIGN_STATUS\2013_08_02_00_11\DesignFiles.txt=Text File
|
|
.\src\DESIGN_STATUS\2013_08_02_00_11\LibrariesList.txt=Text File
|
|
.\src\DESIGN_STATUS\2013_08_02_00_11\synthesis_synthesis.dfml=Text File
|
|
.\src\DESIGN_STATUS\2013_08_02_00_11\implement_ver1_rev1_implementation.dfml=Text File
|
|
|
