| Line 30... |
Line 30... |
|
|
package test_pkg is
|
package test_pkg is
|
|
|
--! Initialising
|
--! Initialising
|
procedure test_init(
|
procedure test_init(
|
fname: in string --! имя файла отчёта
|
fname: in string --! file name for report
|
);
|
);
|
|
|
--! Finished
|
--! Finished
|
procedure test_close;
|
procedure test_close;
|
|
|
|
|
|
--! Read registers
|
|
procedure test_read_reg (
|
|
signal cmd: out bh_cmd; --! command
|
|
signal ret: in bh_ret --! answer
|
|
);
|
|
|
--! Start DMA with incorrect descriptor
|
--! Start DMA with incorrect descriptor
|
procedure test_dsc_incorrect (
|
procedure test_dsc_incorrect (
|
signal cmd: out bh_cmd; --! команда
|
signal cmd: out bh_cmd; --! command
|
signal ret: in bh_ret --! ответ
|
signal ret: in bh_ret --! answer
|
);
|
);
|
|
|
--! Start DMA for one block 4 kB
|
--! Start DMA for one block 4 kB
|
procedure test_read_4kb (
|
procedure test_read_4kb (
|
signal cmd: out bh_cmd; --! команда
|
signal cmd: out bh_cmd; --! command
|
signal ret: in bh_ret --! ответ
|
signal ret: in bh_ret --! answer
|
);
|
);
|
|
|
|
|
--! Read block_test_check 8 kB
|
--! Read block_test_check 8 kB
|
procedure test_adm_read_8kb (
|
procedure test_adm_read_8kb (
|
signal cmd: out bh_cmd; --! команда
|
signal cmd: out bh_cmd; --! command
|
signal ret: in bh_ret --! ответ
|
signal ret: in bh_ret --! answer
|
);
|
);
|
|
|
----! Проверка обращений к блоку MAIN
|
----! Проверка обращений к блоку MAIN
|
--procedure test_block_main (
|
--procedure test_block_main (
|
-- signal cmd: out bh_cmd; --! команда
|
-- signal cmd: out bh_cmd; --! command
|
-- signal ret: in bh_ret --! ответ
|
-- signal ret: in bh_ret --! answer
|
-- );
|
-- );
|
--
|
--
|
----! Чтение 16 кБ с использованием двух блоков дескрипторов
|
----! Чтение 16 кБ с использованием двух блоков дескрипторов
|
--procedure test_adm_read_16kb (
|
--procedure test_adm_read_16kb (
|
-- signal cmd: out bh_cmd; --! команда
|
-- signal cmd: out bh_cmd; --! command
|
-- signal ret: in bh_ret --! ответ
|
-- signal ret: in bh_ret --! answer
|
-- );
|
-- );
|
--
|
--
|
--! Запись 16 кБ с использованием двух блоков дескрипторов
|
--! Запись 16 кБ с использованием двух блоков дескрипторов
|
procedure test_adm_write_16kb (
|
procedure test_adm_write_16kb (
|
signal cmd: out bh_cmd; --! команда
|
signal cmd: out bh_cmd; --! command
|
signal ret: in bh_ret --! ответ
|
signal ret: in bh_ret --! answer
|
);
|
);
|
---------------------------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------------------------
|
--
|
--
|
--
|
--
|
--
|
--
|
procedure test_num_1(
|
procedure test_num_1(
|
signal cmd: out bh_cmd; --! команда
|
signal cmd: out bh_cmd; --! command
|
signal ret: in bh_ret --! ответ
|
signal ret: in bh_ret --! answer
|
);
|
);
|
procedure test_num_2(
|
procedure test_num_2(
|
signal cmd: out bh_cmd; --! команда
|
signal cmd: out bh_cmd; --! command
|
signal ret: in bh_ret --! ответ
|
signal ret: in bh_ret --! answer
|
);
|
);
|
-- ==> TEST_CHECK.WB_CFG_SLAVE
|
-- ==> TEST_CHECK.WB_CFG_SLAVE
|
procedure test_wb_1(
|
procedure test_wb_1(
|
signal cmd: out bh_cmd; --! команда
|
signal cmd: out bh_cmd; --! command
|
signal ret: in bh_ret --! ответ
|
signal ret: in bh_ret --! answer
|
);
|
);
|
-- ==> TEST_GEN.WB_CFG_SLAVE
|
-- ==> TEST_GEN.WB_CFG_SLAVE
|
procedure test_wb_2(
|
procedure test_wb_2(
|
signal cmd: out bh_cmd; --! команда
|
signal cmd: out bh_cmd; --! command
|
signal ret: in bh_ret --! ответ
|
signal ret: in bh_ret --! answer
|
);
|
);
|
end package test_pkg;
|
end package test_pkg;
|
---------------------------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------------------------
|
package body test_pkg is
|
package body test_pkg is
|
|
|
| Line 149... |
Line 154... |
end if;
|
end if;
|
|
|
end test_close;
|
end test_close;
|
|
|
|
|
|
--! Read registers
|
|
procedure test_read_reg (
|
|
signal cmd: out bh_cmd; --! command
|
|
signal ret: in bh_ret --! answer
|
|
)
|
|
is
|
|
|
|
variable adr : std_logic_vector( 31 downto 0 );
|
|
variable data1 : std_logic_vector( 31 downto 0 );
|
|
variable data2 : std_logic_vector( 31 downto 0 );
|
|
variable str : line;
|
|
begin
|
|
|
|
write( str, string'("TEST_READ_REG" ));
|
|
writeline( log, str );
|
|
|
|
block_write( cmd, ret, 0, 8, x"0000000F" ); -- BRD_MODE, reset off
|
|
wait for 100 ns;
|
|
|
|
|
|
--block_read( cmd, ret, 4, 23, x"0000A400" ); -- LOCAL_ADR
|
|
wb_block_gen_read( cmd, ret, REG_BLOCK_ID, data1 ); -- read block id
|
|
wb_block_check_read( cmd, ret, REG_BLOCK_ID, data2 ); -- read block id
|
|
|
|
write( str, string'("BLOCK 0 ID: " )); hwrite( str, data1( 15 downto 0 ) );
|
|
writeline( log, str );
|
|
|
|
write( str, string'("BLOCK 1 ID: " )); hwrite( str, data2( 15 downto 0 ) );
|
|
writeline( log, str );
|
|
|
|
wb_read( cmd, ret, 16#1000#, data1 );
|
|
|
|
wb_read( cmd, ret, 16#3000#, data1 );
|
|
|
|
write( str, string'("0x1000: " )); hwrite( str, data1( 15 downto 0 ) );
|
|
writeline( log, str );
|
|
|
|
write( str, string'("0x3000: " )); hwrite( str, data2( 15 downto 0 ) );
|
|
writeline( log, str );
|
|
|
|
block_write( cmd, ret, 0, 8, x"00000000" ); -- BRD_MODE
|
|
wait for 100 ns;
|
|
block_write( cmd, ret, 0, 8, x"0000000F" ); -- BRD_MODE
|
|
wait for 100 ns;
|
|
|
|
wb_block_gen_read( cmd, ret, REG_BLOCK_ID, data1 ); -- read block id
|
|
wb_block_check_read( cmd, ret, REG_BLOCK_ID, data2 ); -- read block id
|
|
|
|
write( str, string'("BLOCK 0 ID: " )); hwrite( str, data1( 15 downto 0 ) );
|
|
writeline( log, str );
|
|
|
|
write( str, string'("BLOCK 1 ID: " )); hwrite( str, data2( 15 downto 0 ) );
|
|
writeline( log, str );
|
|
|
|
end test_read_reg;
|
|
|
|
|
|
|
|
|
|
|
--! Start DMA with incorrect descriptor
|
--! Start DMA with incorrect descriptor
|
procedure test_dsc_incorrect (
|
procedure test_dsc_incorrect (
|
signal cmd: out bh_cmd; --! команда
|
signal cmd: out bh_cmd; --! command
|
signal ret: in bh_ret --! ответ
|
signal ret: in bh_ret --! answer
|
)
|
)
|
is
|
is
|
|
|
variable adr : std_logic_vector( 31 downto 0 );
|
variable adr : std_logic_vector( 31 downto 0 );
|
variable data : std_logic_vector( 31 downto 0 );
|
variable data : std_logic_vector( 31 downto 0 );
|
| Line 165... |
Line 229... |
begin
|
begin
|
|
|
write( str, string'("TEST_DSC_INCORRECT" ));
|
write( str, string'("TEST_DSC_INCORRECT" ));
|
writeline( log, str );
|
writeline( log, str );
|
|
|
|
block_write( cmd, ret, 0, 8, x"0000000F" ); -- BRD_MODE, reset off
|
|
wait for 100 ns;
|
|
|
---- Init block of descriptor ---
|
---- Init block of descriptor ---
|
for ii in 0 to 127 loop
|
for ii in 0 to 127 loop
|
adr:= x"00100000";
|
adr:= x"00100000";
|
adr:=adr + ii*4;
|
adr:=adr + ii*4;
|
int_mem_write( cmd, ret, adr, x"00000000" );
|
int_mem_write( cmd, ret, adr, x"00000000" );
|
| Line 207... |
Line 274... |
end test_dsc_incorrect;
|
end test_dsc_incorrect;
|
|
|
|
|
--! Start DMA for one block 4 kB
|
--! Start DMA for one block 4 kB
|
procedure test_read_4kb (
|
procedure test_read_4kb (
|
signal cmd: out bh_cmd; --! команда
|
signal cmd: out bh_cmd; --! command
|
signal ret: in bh_ret --! ответ
|
signal ret: in bh_ret --! answer
|
)
|
)
|
is
|
is
|
|
|
variable adr : std_logic_vector( 31 downto 0 );
|
variable adr : std_logic_vector( 31 downto 0 );
|
variable data : std_logic_vector( 31 downto 0 );
|
variable data : std_logic_vector( 31 downto 0 );
|
| Line 224... |
Line 291... |
begin
|
begin
|
|
|
write( str, string'("TEST_READ_4KB" ));
|
write( str, string'("TEST_READ_4KB" ));
|
writeline( log, str );
|
writeline( log, str );
|
|
|
|
block_write( cmd, ret, 0, 8, x"0000000F" ); -- BRD_MODE, reset off
|
|
wait for 100 ns;
|
|
|
|
|
---- Init block of descriptor ---
|
---- Init block of descriptor ---
|
for ii in 0 to 127 loop
|
for ii in 0 to 127 loop
|
adr:= x"00100000";
|
adr:= x"00100000";
|
adr:=adr + ii*4;
|
adr:=adr + ii*4;
|
int_mem_write( cmd, ret, adr, x"00000000" );
|
int_mem_write( cmd, ret, adr, x"00000000" );
|
| Line 359... |
Line 430... |
end test_read_4kb;
|
end test_read_4kb;
|
|
|
|
|
--! Read block_test_check 8 kB
|
--! Read block_test_check 8 kB
|
procedure test_adm_read_8kb (
|
procedure test_adm_read_8kb (
|
signal cmd: out bh_cmd; --! команда
|
signal cmd: out bh_cmd; --! command
|
signal ret: in bh_ret --! ответ
|
signal ret: in bh_ret --! answer
|
)
|
)
|
is
|
is
|
|
|
variable adr : std_logic_vector( 31 downto 0 );
|
variable adr : std_logic_vector( 31 downto 0 );
|
variable data : std_logic_vector( 31 downto 0 );
|
variable data : std_logic_vector( 31 downto 0 );
|
variable str : line;
|
variable str : line;
|
|
|
variable error : integer:=0;
|
variable error : integer:=0;
|
variable dma_complete : integer;
|
variable dma_complete : integer;
|
|
|
|
variable status : std_logic_vector( 31 downto 0 );
|
|
variable reg_block_wr : std_logic_vector( 31 downto 0 );
|
|
|
begin
|
begin
|
|
|
write( str, string'("TEST_ADM_READ_8KB" ));
|
write( str, string'("TEST_ADM_READ_8KB" ));
|
writeline( log, str );
|
writeline( log, str );
|
|
|
|
block_write( cmd, ret, 0, 8, x"0000000F" ); -- BRD_MODE, reset off
|
|
wait for 100 ns;
|
|
|
---- Init block of descriptor ---
|
---- Init block of descriptor ---
|
for ii in 0 to 127 loop
|
for ii in 0 to 127 loop
|
adr:= x"00100000";
|
adr:= x"00100000";
|
adr:=adr + ii*4;
|
adr:=adr + ii*4;
|
int_mem_write( cmd, ret, adr, x"00000000" );
|
int_mem_write( cmd, ret, adr, x"00000000" );
|
| Line 397... |
Line 474... |
int_mem_write( cmd, ret, x"001001F8", x"00000000" );
|
int_mem_write( cmd, ret, x"001001F8", x"00000000" );
|
int_mem_write( cmd, ret, x"001001FC", x"D6644953" );
|
int_mem_write( cmd, ret, x"001001FC", x"D6644953" );
|
|
|
|
|
---- Программирование канала DMA ----
|
---- Программирование канала DMA ----
|
block_write( cmd, ret, 4, 8, x"00000027" ); -- DMA_MODE
|
block_write( cmd, ret, 5, 8, x"00000027" ); -- DMA_MODE
|
block_write( cmd, ret, 4, 9, x"00000010" ); -- DMA_CTRL - RESET FIFO
|
block_write( cmd, ret, 5, 9, x"00000010" ); -- DMA_CTRL - RESET FIFO
|
|
|
block_write( cmd, ret, 4, 20, x"00100000" ); -- PCI_ADRL
|
block_write( cmd, ret, 5, 20, x"00100000" ); -- PCI_ADRL
|
block_write( cmd, ret, 4, 21, x"00100000" ); -- PCI_ADRH
|
block_write( cmd, ret, 5, 21, x"00100000" ); -- PCI_ADRH
|
block_write( cmd, ret, 4, 23, TEST_GEN_WB_BURST_SLAVE ); -- LOCAL_ADR
|
block_write( cmd, ret, 5, 23, TEST_GEN_WB_BURST_SLAVE ); -- LOCAL_ADR
|
|
|
|
|
wb_block_gen_write( cmd, ret, REG_TEST_GEN_CTRL, x"00000001" ); -- reset
|
wb_block_gen_write( cmd, ret, REG_TEST_GEN_CTRL, x"00000001" ); -- reset
|
wb_block_gen_write( cmd, ret, REG_TEST_GEN_CTRL, x"00000000" );
|
wb_block_gen_write( cmd, ret, REG_TEST_GEN_CTRL, x"00000000" );
|
wb_block_gen_read( cmd, ret, REG_BLOCK_ID, data ); -- read block id
|
wb_block_gen_read( cmd, ret, REG_BLOCK_ID, data ); -- read block id
|
| Line 414... |
Line 491... |
hwrite( str, data );
|
hwrite( str, data );
|
writeline( log, str );
|
writeline( log, str );
|
|
|
wb_block_gen_write( cmd, ret, REG_TEST_GEN_SIZE, x"00000001" ); -- size of block = 4 kByte
|
wb_block_gen_write( cmd, ret, REG_TEST_GEN_SIZE, x"00000001" ); -- size of block = 4 kByte
|
|
|
block_write( cmd, ret, 4, 9, x"00000001" ); -- DMA_CTRL - START
|
block_write( cmd, ret, 5, 9, x"00000001" ); -- DMA_CTRL - START
|
|
|
|
wb_block_gen_read( cmd, ret, REG_TEST_GEN_STATUS, status ); -- read status
|
|
write( str, string'("WB_GEN_STATUS: " )); hwrite( str, status( 31 downto 0 ) ); writeline( log, str );
|
|
wb_block_gen_read( cmd, ret, REG_TEST_GEN_BL_WR, reg_block_wr ); -- read block_wr
|
|
write( str, string'("WB_GEN_BL_WR: " )); hwrite( str, reg_block_wr( 31 downto 0 ) ); writeline( log, str );
|
|
|
|
|
wb_block_gen_write( cmd, ret, REG_TEST_GEN_CTRL, x"000006A0" ); -- start test sequence
|
wb_block_gen_write( cmd, ret, REG_TEST_GEN_CTRL, x"000006A0" ); -- start test sequence
|
|
|
wait for 20 us;
|
wait for 20 us;
|
|
|
block_read( cmd, ret, 4, 16, data ); -- STATUS
|
block_read( cmd, ret, 5, 16, data ); -- STATUS
|
|
|
write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
|
write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
|
if( data( 8 )='1' ) then
|
if( data( 8 )='1' ) then
|
write( str, string'(" - descriptor is correct" ));
|
write( str, string'(" - descriptor is correct" ));
|
else
|
else
|
| Line 438... |
Line 521... |
|
|
---- Ожидание завершения DMA ----
|
---- Ожидание завершения DMA ----
|
dma_complete := 0;
|
dma_complete := 0;
|
for ii in 0 to 100 loop
|
for ii in 0 to 100 loop
|
|
|
block_read( cmd, ret, 4, 16, data ); -- STATUS
|
block_read( cmd, ret, 5, 16, data ); -- STATUS
|
write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
|
write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
|
if( data(5)='1' ) then
|
if( data(5)='1' ) then
|
write( str, string'(" - DMA finished " ));
|
write( str, string'(" - DMA finished " ));
|
dma_complete := 1;
|
dma_complete := 1;
|
|
|
block_write( cmd, ret, 4, 16#11#, x"00000010" ); -- FLAG_CLR - reset EOT
|
block_write( cmd, ret, 5, 16#11#, x"00000010" ); -- FLAG_CLR - reset EOT
|
|
|
end if;
|
end if;
|
writeline( log, str );
|
writeline( log, str );
|
|
|
if( dma_complete=1 ) then
|
if( dma_complete=1 ) then
|
| Line 467... |
Line 550... |
error:=error+1;
|
error:=error+1;
|
end if;
|
end if;
|
|
|
end if;
|
end if;
|
|
|
|
wb_block_gen_read( cmd, ret, REG_TEST_GEN_STATUS, status ); -- read status
|
|
write( str, string'("WB_GEN_STATUS: " )); hwrite( str, status( 31 downto 0 ) ); writeline( log, str );
|
|
wb_block_gen_read( cmd, ret, REG_TEST_GEN_BL_WR, reg_block_wr ); -- read block_wr
|
|
write( str, string'("WB_GEN_BL_WR: " )); hwrite( str, reg_block_wr( 31 downto 0 ) ); writeline( log, str );
|
|
|
|
|
for ii in 0 to 3 loop
|
for ii in 0 to 3 loop
|
|
|
block_read( cmd, ret, 4, 16, data ); -- STATUS
|
block_read( cmd, ret, 5, 16, data ); -- STATUS
|
write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
|
write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
|
writeline( log, str );
|
writeline( log, str );
|
wait for 500 ns;
|
wait for 500 ns;
|
|
|
end loop;
|
end loop;
|
|
|
|
|
block_write( cmd, ret, 4, 9, x"00000000" ); -- DMA_CTRL - STOP
|
block_write( cmd, ret, 5, 9, x"00000000" ); -- DMA_CTRL - STOP
|
|
|
write( str, string'(" Block 0 - read: " ));
|
write( str, string'(" Block 0 - read: " ));
|
writeline( log, str );
|
writeline( log, str );
|
|
|
for ii in 0 to 15 loop
|
for ii in 0 to 15 loop
|
| Line 531... |
Line 620... |
end test_adm_read_8kb;
|
end test_adm_read_8kb;
|
--
|
--
|
--
|
--
|
----! Проверка обращений к блоку MAIN
|
----! Проверка обращений к блоку MAIN
|
--procedure test_block_main (
|
--procedure test_block_main (
|
-- signal cmd: out bh_cmd; --! команда
|
-- signal cmd: out bh_cmd; --! command
|
-- signal ret: in bh_ret --! ответ
|
-- signal ret: in bh_ret --! answer
|
-- )
|
-- )
|
--is
|
--is
|
--
|
--
|
--variable adr : std_logic_vector( 31 downto 0 );
|
--variable adr : std_logic_vector( 31 downto 0 );
|
--variable data : std_logic_vector( 31 downto 0 );
|
--variable data : std_logic_vector( 31 downto 0 );
|
| Line 616... |
Line 705... |
--
|
--
|
--
|
--
|
--
|
--
|
----! Чтение 16 кБ с использованием двух блоков дескрипторов
|
----! Чтение 16 кБ с использованием двух блоков дескрипторов
|
--procedure test_adm_read_16kb (
|
--procedure test_adm_read_16kb (
|
-- signal cmd: out bh_cmd; --! команда
|
-- signal cmd: out bh_cmd; --! command
|
-- signal ret: in bh_ret --! ответ
|
-- signal ret: in bh_ret --! answer
|
-- )
|
-- )
|
--is
|
--is
|
--
|
--
|
--variable adr : std_logic_vector( 31 downto 0 );
|
--variable adr : std_logic_vector( 31 downto 0 );
|
--variable data : std_logic_vector( 31 downto 0 );
|
--variable data : std_logic_vector( 31 downto 0 );
|
| Line 867... |
Line 956... |
--
|
--
|
--
|
--
|
--
|
--
|
--! Запись 16 кБ с использованием двух блоков дескрипторов
|
--! Запись 16 кБ с использованием двух блоков дескрипторов
|
procedure test_adm_write_16kb (
|
procedure test_adm_write_16kb (
|
signal cmd: out bh_cmd; --! команда
|
signal cmd: out bh_cmd; --! command
|
signal ret: in bh_ret --! ответ
|
signal ret: in bh_ret --! answer
|
)
|
)
|
is
|
is
|
|
|
variable adr : std_logic_vector( 31 downto 0 );
|
variable adr : std_logic_vector( 31 downto 0 );
|
variable data : std_logic_vector( 31 downto 0 );
|
variable data : std_logic_vector( 31 downto 0 );
|
| Line 889... |
Line 978... |
begin
|
begin
|
|
|
write( str, string'("TEST_ADM_WRITE_16KB" ));
|
write( str, string'("TEST_ADM_WRITE_16KB" ));
|
writeline( log, str );
|
writeline( log, str );
|
|
|
|
block_write( cmd, ret, 0, 8, x"0000000F" ); -- BRD_MODE, reset off
|
|
wait for 100 ns;
|
|
|
---- Формирование блока дескрипторов ---
|
---- Формирование блока дескрипторов ---
|
for ii in 0 to 256 loop
|
for ii in 0 to 256 loop
|
adr:= x"00100000";
|
adr:= x"00100000";
|
adr:=adr + ii*4;
|
adr:=adr + ii*4;
|
int_mem_write( cmd, ret, adr, x"00000000" );
|
int_mem_write( cmd, ret, adr, x"00000000" );
|
| Line 1296... |
Line 1388... |
---------------------------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------------------------
|
--
|
--
|
-- My procedure for test Updated Design (test_read_4kb like refenernce)
|
-- My procedure for test Updated Design (test_read_4kb like refenernce)
|
--
|
--
|
procedure test_num_1 (
|
procedure test_num_1 (
|
signal cmd: out bh_cmd; --! команда
|
signal cmd: out bh_cmd; --! command
|
signal ret: in bh_ret --! ответ
|
signal ret: in bh_ret --! answer
|
) is
|
) is
|
|
|
variable adr : std_logic_vector( 31 downto 0 );
|
variable adr : std_logic_vector( 31 downto 0 );
|
variable data : std_logic_vector( 31 downto 0 );
|
variable data : std_logic_vector( 31 downto 0 );
|
variable str : line;
|
variable str : line;
|
| Line 1433... |
Line 1525... |
end test_num_1;
|
end test_num_1;
|
--
|
--
|
--
|
--
|
--
|
--
|
procedure test_num_2 (
|
procedure test_num_2 (
|
signal cmd: out bh_cmd; --! команда
|
signal cmd: out bh_cmd; --! command
|
signal ret: in bh_ret --! ответ
|
signal ret: in bh_ret --! answer
|
) is
|
) is
|
|
|
variable adr : std_logic_vector( 31 downto 0 );
|
variable adr : std_logic_vector( 31 downto 0 );
|
variable data : std_logic_vector( 31 downto 0 );
|
variable data : std_logic_vector( 31 downto 0 );
|
variable data64 : std_logic_vector( 63 downto 0 );
|
variable data64 : std_logic_vector( 63 downto 0 );
|
| Line 1584... |
Line 1676... |
--
|
--
|
-- My procedure for test WB stuff in Design:
|
-- My procedure for test WB stuff in Design:
|
-- ==> TEST_CHECK.WB_CFG_SLAVE
|
-- ==> TEST_CHECK.WB_CFG_SLAVE
|
--
|
--
|
procedure test_wb_1 (
|
procedure test_wb_1 (
|
signal cmd: out bh_cmd; --! команда
|
signal cmd: out bh_cmd; --! command
|
signal ret: in bh_ret --! ответ
|
signal ret: in bh_ret --! answer
|
) is
|
) is
|
|
|
variable adr : std_logic_vector( 31 downto 0 );
|
variable adr : std_logic_vector( 31 downto 0 );
|
variable data32 : std_logic_vector( 31 downto 0 );
|
variable data32 : std_logic_vector( 31 downto 0 );
|
variable data64 : std_logic_vector( 63 downto 0 );
|
variable data64 : std_logic_vector( 63 downto 0 );
|
| Line 1747... |
Line 1839... |
--
|
--
|
-- My procedure for test WB stuff in Design:
|
-- My procedure for test WB stuff in Design:
|
-- ==> TEST_GEN.WB_CFG_SLAVE
|
-- ==> TEST_GEN.WB_CFG_SLAVE
|
--
|
--
|
procedure test_wb_2 (
|
procedure test_wb_2 (
|
signal cmd: out bh_cmd; --! команда
|
signal cmd: out bh_cmd; --! command
|
signal ret: in bh_ret --! ответ
|
signal ret: in bh_ret --! answer
|
) is
|
) is
|
|
|
variable adr : std_logic_vector( 31 downto 0 );
|
variable adr : std_logic_vector( 31 downto 0 );
|
variable data32 : std_logic_vector( 31 downto 0 );
|
variable data32 : std_logic_vector( 31 downto 0 );
|
variable data64 : std_logic_vector( 63 downto 0 );
|
variable data64 : std_logic_vector( 63 downto 0 );
|
