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Line 53... |
--
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--
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constant REG_TEST_GEN_CTRL : integer:=8;
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constant REG_TEST_GEN_CTRL : integer:=8;
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constant REG_TEST_GEN_SIZE : integer:=9;
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constant REG_TEST_GEN_SIZE : integer:=9;
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constant REG_TEST_GEN_CNT1 : integer:=16#0A#;
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constant REG_TEST_GEN_CNT1 : integer:=16#0A#;
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constant REG_TEST_GEN_CNT2 : integer:=16#0B#;
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constant REG_TEST_GEN_CNT2 : integer:=16#0B#;
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constant REG_TEST_GEN_STATUS : integer:=16#10#;
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constant REG_TEST_GEN_BL_WR : integer:=16#11#;
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constant REG_TEST_GEN_BL_WR : integer:=16#11#;
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--
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--
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-- Define SoPC ADDR (must be EQU to: ...\src\top\sp605_lx45t_wishbone_sopc_wb.vhd)
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-- Define SoPC ADDR (must be EQU to: ...\src\top\sp605_lx45t_wishbone_sopc_wb.vhd)
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--
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--
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constant TEST_CHECK_WB_CFG_SLAVE : std_logic_vector( 31 downto 0) := x"20000000";
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constant TEST_CHECK_WB_CFG_SLAVE : std_logic_vector( 31 downto 0) := x"20000000";
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constant TEST_CHECK_WB_BURST_SLAVE : std_logic_vector( 31 downto 0) := x"20001000"; -- check data: write-only
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constant TEST_CHECK_WB_BURST_SLAVE : std_logic_vector( 31 downto 0) := x"20001000"; -- check data: write-only
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constant TEST_GEN_WB_CFG_SLAVE : std_logic_vector( 31 downto 0) := x"20002000";
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constant TEST_GEN_WB_CFG_SLAVE : std_logic_vector( 31 downto 0) := x"20002000";
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constant TEST_GEN_WB_BURST_SLAVE : std_logic_vector( 31 downto 0) := x"20003000"; -- generate data: read-only
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constant TEST_GEN_WB_BURST_SLAVE : std_logic_vector( 31 downto 0) := x"20003000"; -- generate data: read-only
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---- Write to wishbone ----
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procedure wb_write (
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signal cmd: out bh_cmd; -- команда
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signal ret: in bh_ret; -- ответ
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adr: in integer; -- номер регистра
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data: in std_logic_vector( 31 downto 0 ) -- данные
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);
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---- Read from wishbone ----
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procedure wb_read (
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signal cmd: out bh_cmd; -- команда для ADSP
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signal ret: in bh_ret; -- ответ ADSP
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adr: in integer; -- номер регистра
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data: out std_logic_vector( 31 downto 0 ) -- данные
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);
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---- Запись в регистр блока TEST_CHECK.WB_CFG_SLAVE ----
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---- Запись в регистр блока TEST_CHECK.WB_CFG_SLAVE ----
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procedure wb_block_check_write (
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procedure wb_block_check_write (
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signal cmd: out bh_cmd; -- команда
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signal cmd: out bh_cmd; -- команда
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signal ret: in bh_ret; -- ответ
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signal ret: in bh_ret; -- ответ
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Line 122... |
end package wb_block_pkg;
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end package wb_block_pkg;
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---------------------------------------------------------------------------------------------------
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---------------------------------------------------------------------------------------------------
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package body wb_block_pkg is
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package body wb_block_pkg is
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---- Write to wishbone ----
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procedure wb_write (
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signal cmd: out bh_cmd; -- команда
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signal ret: in bh_ret; -- ответ
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adr: in integer; -- номер регистра
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data: in std_logic_vector( 31 downto 0 ) -- данные
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) is
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begin
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data_write( cmd, ret, TEST_CHECK_WB_CFG_SLAVE+conv_std_logic_vector(adr, 32), data );
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end;
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---- Read from wishbone ----
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procedure wb_read (
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signal cmd: out bh_cmd; -- команда для ADSP
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signal ret: in bh_ret; -- ответ ADSP
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adr: in integer; -- номер регистра
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data: out std_logic_vector( 31 downto 0 ) -- данные
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) is
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begin
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data_read( cmd, ret, TEST_CHECK_WB_CFG_SLAVE+conv_std_logic_vector(adr, 32), data );
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end;
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---- Запись в регистр блока TEST_CHECK.WB_CFG_SLAVE ----
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---- Запись в регистр блока TEST_CHECK.WB_CFG_SLAVE ----
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procedure wb_block_check_write (
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procedure wb_block_check_write (
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signal cmd: out bh_cmd; -- команда
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signal cmd: out bh_cmd; -- команда
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signal ret: in bh_ret; -- ответ
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signal ret: in bh_ret; -- ответ
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reg: in integer; -- номер регистра
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reg: in integer; -- номер регистра
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