| Line 77... |
Line 77... |
deviceID = ReadOperationWordReg(brd, PEMAINadr_DEVICE_ID);
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deviceID = ReadOperationWordReg(brd, PEMAINadr_DEVICE_ID);
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deviceRev = ReadOperationWordReg(brd, PEMAINadr_DEVICE_REV);
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deviceRev = ReadOperationWordReg(brd, PEMAINadr_DEVICE_REV);
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dbg_msg(dbg_trace, "%s(): DeviceID = 0x%X, DeviceRev = 0x%X.\n", __FUNCTION__, deviceID, deviceRev);
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dbg_msg(dbg_trace, "%s(): DeviceID = 0x%X, DeviceRev = 0x%X.\n", __FUNCTION__, deviceID, deviceRev);
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pci_set_dma_mask(brd->m_pci, DMA_BIT_MASK(32));
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temp = ReadOperationWordReg(brd, PEMAINadr_PLD_VER);
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temp = ReadOperationWordReg(brd, PEMAINadr_PLD_VER);
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dbg_msg(dbg_trace, "%s(): PldVER = 0x%X.\n", __FUNCTION__, temp);
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dbg_msg(dbg_trace, "%s(): PldVER = 0x%X.\n", __FUNCTION__, temp);
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| Line 444... |
Line 444... |
//--------------------------------------------------------------------
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//--------------------------------------------------------------------
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|
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int DmaEnable(struct pex_device *brd, u32 AdmNumber, u32 TetrNumber)
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int DmaEnable(struct pex_device *brd, u32 AdmNumber, u32 TetrNumber)
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{
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{
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int Status = 0;
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int Status = 0;
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//u32 Value = 0;
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u32 Value = 0;
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//Status = ReadRegData(brd, AdmNumber, TetrNumber, 0, &Value);
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Status = ReadRegData(brd, AdmNumber, TetrNumber, 0, &Value);
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//if(Status != 0) return Status;
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if(Status != 0) return Status;
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//Value |= 0x8; // DRQ enable
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Value |= 0x8; // DRQ enable
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//Status = WriteRegData(brd, AdmNumber, TetrNumber, 0, Value);
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Status = WriteRegData(brd, AdmNumber, TetrNumber, 0, Value);
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//err_msg(err_trace, "%s: MODE0 = 0x%X.\n", __FUNCTION__, Value);
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//err_msg(err_trace, "%s: MODE0 = 0x%X.\n", __FUNCTION__, Value);
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return Status;
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return Status;
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}
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}
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//--------------------------------------------------------------------
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//--------------------------------------------------------------------
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|
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int DmaDisable(struct pex_device *brd, u32 AdmNumber, u32 TetrNumber)
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int DmaDisable(struct pex_device *brd, u32 AdmNumber, u32 TetrNumber)
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{
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{
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int Status = 0;
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int Status = 0;
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//u32 Value = 0;
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u32 Value = 0;
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//Status = ReadRegData(brd, AdmNumber, TetrNumber, 0, &Value);
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Status = ReadRegData(brd, AdmNumber, TetrNumber, 0, &Value);
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//if(Status != 0) return Status;
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if(Status != 0) return Status;
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//Value &= 0xfff7; // DRQ disable
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Value &= 0xfff7; // DRQ disable
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//Status = WriteRegData(brd, AdmNumber, TetrNumber, 0, Value);
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Status = WriteRegData(brd, AdmNumber, TetrNumber, 0, Value);
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return Status;
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return Status;
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}
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}
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|
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//--------------------------------------------------------------------
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//--------------------------------------------------------------------
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|
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| Line 503... |
Line 503... |
int Status = 0;
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int Status = 0;
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u32 FifoAddr = brd->m_FifoAddr[NumberOfChannel];
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u32 FifoAddr = brd->m_FifoAddr[NumberOfChannel];
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CtrlExt.AsWhole = ReadOperationWordReg(brd, PEFIFOadr_DMA_CTRL + FifoAddr);
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CtrlExt.AsWhole = ReadOperationWordReg(brd, PEFIFOadr_DMA_CTRL + FifoAddr);
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CtrlExt.ByBits.Pause = 0;
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CtrlExt.ByBits.Pause = 0;
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|
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//printk("<0>%s(): CtrlExt.AsWhole = 0x%x\n", __FUNCTION__, CtrlExt.AsWhole);
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//printk("%s(): CtrlExt.AsWhole = 0x%x\n", __FUNCTION__, CtrlExt.AsWhole);
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|
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WriteOperationWordReg(brd, PEFIFOadr_DMA_CTRL + FifoAddr, CtrlExt.AsWhole);
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WriteOperationWordReg(brd, PEFIFOadr_DMA_CTRL + FifoAddr, CtrlExt.AsWhole);
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|
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return Status;
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return Status;
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}
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}
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| Line 520... |
Line 520... |
u64 SGTableAddress;
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u64 SGTableAddress;
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u32 LocalAddress, DmaDirection;
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u32 LocalAddress, DmaDirection;
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u32 adm_num, tetr_num;
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u32 adm_num, tetr_num;
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u32 FifoAddr = brd->m_FifoAddr[NumberOfChannel];
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u32 FifoAddr = brd->m_FifoAddr[NumberOfChannel];
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|
|
dbg_msg(dbg_trace, "%s(): channel = %d, FifoAddr = 0x%04X.\n",__FUNCTION__, NumberOfChannel, FifoAddr);
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dbg_msg(err_trace, "%s(): channel = %d, FifoAddr = 0x%04X.\n",__FUNCTION__, NumberOfChannel, FifoAddr);
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|
|
DmaCtrl.AsWhole = 0;
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DmaCtrl.AsWhole = 0;
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WriteOperationWordReg(brd, PEFIFOadr_DMA_CTRL + FifoAddr, DmaCtrl.AsWhole);
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WriteOperationWordReg(brd, PEFIFOadr_DMA_CTRL + FifoAddr, DmaCtrl.AsWhole);
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if(brd->m_BlockFifoId[NumberOfChannel] == PE_EXT_FIFO_ID)
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if(brd->m_BlockFifoId[NumberOfChannel] == PE_EXT_FIFO_ID)
|
{
|
{
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| Line 566... |
Line 566... |
dbg_msg(dbg_trace, "%s(): channel = %d, DMA_CTRL_EXT = 0x%04X.\n", __FUNCTION__, NumberOfChannel, CtrlExt.AsWhole);
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dbg_msg(dbg_trace, "%s(): channel = %d, DMA_CTRL_EXT = 0x%04X.\n", __FUNCTION__, NumberOfChannel, CtrlExt.AsWhole);
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}
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}
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|
|
adm_num = GetAdmNum(brd->m_DmaChannel[NumberOfChannel]);
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adm_num = GetAdmNum(brd->m_DmaChannel[NumberOfChannel]);
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tetr_num = GetTetrNum(brd->m_DmaChannel[NumberOfChannel]);
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tetr_num = GetTetrNum(brd->m_DmaChannel[NumberOfChannel]);
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//Status = DmaEnable(brd, adm_num, tetr_num);
|
Status = DmaEnable(brd, adm_num, tetr_num);
|
|
|
return Status;
|
return Status;
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}
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}
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|
|
//--------------------------------------------------------------------
|
//--------------------------------------------------------------------
|
| Line 581... |
Line 581... |
u32 FifoAddr = brd->m_FifoAddr[NumberOfChannel];
|
u32 FifoAddr = brd->m_FifoAddr[NumberOfChannel];
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int enbl = 0;
|
int enbl = 0;
|
int i = 0;
|
int i = 0;
|
u32 tetr_num;
|
u32 tetr_num;
|
|
|
|
dbg_msg(err_trace, "%s(): channel = %d, FifoAddr = 0x%04X.\n",__FUNCTION__, NumberOfChannel, FifoAddr);
|
|
|
if(brd->m_BlockFifoId[NumberOfChannel] == PE_EXT_FIFO_ID)
|
if(brd->m_BlockFifoId[NumberOfChannel] == PE_EXT_FIFO_ID)
|
{
|
{
|
DMA_CTRL_EXT CtrlExt;
|
DMA_CTRL_EXT CtrlExt;
|
DMA_MODE_EXT ModeExt;
|
DMA_MODE_EXT ModeExt;
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|
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| Line 602... |
Line 604... |
if(brd->m_DmaChanEnbl[i])
|
if(brd->m_DmaChanEnbl[i])
|
enbl = 1;
|
enbl = 1;
|
brd->m_DmaIrqEnbl = enbl;
|
brd->m_DmaIrqEnbl = enbl;
|
|
|
tetr_num = GetTetrNum(brd->m_DmaChannel[NumberOfChannel]);
|
tetr_num = GetTetrNum(brd->m_DmaChannel[NumberOfChannel]);
|
//Status = DmaDisable(brd, 0, tetr_num);
|
Status = DmaDisable(brd, 0, tetr_num);
|
CompleteDmaTransfer(brd->m_DmaChannel[NumberOfChannel]);
|
CompleteDmaTransfer(brd->m_DmaChannel[NumberOfChannel]);
|
|
|
return Status;
|
return Status;
|
}
|
}
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|
