0. This directory contains simulation environment for the sg_pcie_dma design.
0. This directory contains simulation environment for the pcie_sg_dma design.
tf64_pcie_trn.v is the simulation file in Verilog HDL.
tf64_pcie_trn.v is the simulation file in Verilog HDL.
sg_sim.mpf is the ModelSim project file. So your ModelSim version has to support mixed HDL because the design files are mostly written in VHDL. If you want to help in translating this simulation into VHDL, contact me via
sg_sim.mpf is the ModelSim project file. So your ModelSim version has to support mixed HDL because the design files are mostly written in VHDL. If you want to help in translating this simulation into VHDL, contact me via
weng.ziti@gmail.com. Thanks in advance.
weng.ziti@gmail.com. Thanks in advance.
1. To start the simulation, open the sg_sim.mpf in ModelSim, and simulate the tf64_pcie_trn.v after compiling the work library.
1. To start the simulation, open the sg_sim.mpf in ModelSim, and simulate the tf64_pcie_trn.v after compiling the work library.
