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[/] [pit/] [trunk/] [bench/] [sys_verilog/] [tst_bench_top.sv] - Diff between revs 23 and 24

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Line 34... Line 34... 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
////////////////////////////////////////////////////////////////////////////////
 
////////////////////////////////////////////////////////////////////////////////
 
// 45678901234567890123456789012345678901234567890123456789012345678901234567890
 
// 45678901234567890123456789012345678901234567890123456789012345678901234567890
 
 
 
 
 
 
 
 
 
`include "timescale.v"
 
`include "timescale.v"
 
 
 
 
 
module tst_bench_top();
 
module tst_bench_top();
 
 
 
 
 
  parameter STOP_ON_ERROR = 1'b0;
 
  parameter STOP_ON_ERROR = 1'b0;
Line 66... Line 65... 
  logic [15:0] error_count;
 
  logic [15:0] error_count;
 
 
 
 
 
  logic scl, scl0_o, scl0_oen, scl1_o, scl1_oen;
 
  logic scl, scl0_o, scl0_oen, scl1_o, scl1_oen;
 
  logic sda, sda0_o, sda0_oen, sda1_o, sda1_oen;
 
  logic sda, sda0_o, sda0_oen, sda1_o, sda1_oen;
 
 
 
 
 
  // Name Address Locations
 
  // Name the Address Locations of the PIT Wishbone control registers
 
  parameter PIT_CNTRL = 5'b0_0000;
 
  parameter PIT_CNTRL = 5'b0_0000;
 
  parameter PIT_MOD   = 5'b0_0001;
 
  parameter PIT_MOD   = 5'b0_0001;
 
  parameter PIT_COUNT = 5'b0_0010;
 
  parameter PIT_COUNT = 5'b0_0010;
 
 
 
 
 
  parameter RD      = 1'b1;
 
  parameter RD      = 1'b1;
Line 78... Line 77... 
  parameter SADR    = 7'b0010_000;
 
  parameter SADR    = 7'b0010_000;
 
 
 
 
 
  parameter CTR_EN  = 8'b1000_0000;  // core enable bit
 
  parameter CTR_EN  = 8'b1000_0000;  // core enable bit
 
  parameter CTR_IEN = 8'b0100_0000;  // core interrupt enable bit
 
  parameter CTR_IEN = 8'b0100_0000;  // core interrupt enable bit
 
 
 
 
 
 
 
  // Name the control/status bits of the PIT registers
 
  parameter PIT_CNTRL_SLAVE  = 16'h8000;  // PIT Slave mode
 
  parameter PIT_CNTRL_SLAVE  = 16'h8000;  // PIT Slave mode
 
  parameter PIT_CNTRL_FLAG   = 16'h0004;  // PIT Rollover Flag
 
  parameter PIT_CNTRL_FLAG   = 16'h0004;  // PIT Rollover Flag
 
  parameter PIT_CNTRL_IRQEN  = 16'h0002;  // PIT Interupt Enable
 
  parameter PIT_CNTRL_IRQEN  = 16'h0002;  // PIT Interupt Enable
 
  parameter PIT_CNTRL_ENA    = 16'h0001;  // PIT Enable
 
  parameter PIT_CNTRL_ENA    = 16'h0001;  // PIT Enable
 
 
 
 
 
  parameter SLAVE_0_CNTRL = 5'b0_1000;
 
  parameter SLAVE_0_CNTRL = 5'b0_1000 + PIT_CNTRL;
 
  parameter SLAVE_0_MOD   = 5'b0_1001;
 
  parameter SLAVE_0_MOD   = 5'b0_1000 + PIT_MOD;
 
  parameter SLAVE_0_COUNT = 5'b0_1010;
 
  parameter SLAVE_0_COUNT = 5'b0_1000 + PIT_COUNT;
 
 
 
 
 
  parameter SLAVE_1_CNTRL = 5'b1_0000;
 
  parameter SLAVE_1_CNTRL = 5'b1_0000 + PIT_CNTRL;
 
  parameter SLAVE_1_MOD   = 5'b1_0001;
 
  parameter SLAVE_1_MOD   = 5'b1_0000 + PIT_MOD;
 
  parameter SLAVE_1_COUNT = 5'b1_0010;
 
  parameter SLAVE_1_COUNT = 5'b1_0000 + PIT_COUNT;
 
 
 
 
 
  parameter SLAVE_2_CNTRL_0 = 5'b1_1000;
 
  parameter SLAVE_2_CNTRL_0 = 5'b1_1000;
 
  parameter SLAVE_2_CNTRL_1 = 5'b1_1001;
 
  parameter SLAVE_2_CNTRL_1 = 5'b1_1001;
 
  parameter SLAVE_2_MOD_0   = 5'b1_1010;
 
  parameter SLAVE_2_MOD_0   = 5'b1_1010;
 
  parameter SLAVE_2_MOD_1   = 5'b1_1011;
 
  parameter SLAVE_2_MOD_1   = 5'b1_1011;
Line 101... Line 101... 
  parameter SLAVE_2_COUNT_1 = 5'b1_1101;
 
  parameter SLAVE_2_COUNT_1 = 5'b1_1101;
 
 
 
 
 
  // initial values and testbench setup
 
  // initial values and testbench setup
 
  initial
 
  initial
 
    begin
 
    begin
 
      mstr_test_clk = 0;
 
      mstr_test_clk <= 0;
 
      vector = 0;
 
      vector        <= 0;
 
      test_num = 0;
 
      test_num      <= 0;
 
      error_count = 0;
 
      error_count   <= 0;
 
 
 
 
 
      `ifdef WAVES
 
      `ifdef WAVES
 
           $shm_open("waves");
 
           $shm_open("waves");
 
           $shm_probe("AS",tst_bench_top,"AS");
 
           $shm_probe("AS",tst_bench_top,"AS");
 
           $display("\nINFO: Signal dump enabled ...\n\n");
 
           $display("\nINFO: Signal dump enabled ...\n\n");
Line 143... Line 143... 
          wrap_up;
 
          wrap_up;
 
        end
 
        end
 
    end
 
    end
 
 
 
 
 
  // Add up errors tha come from WISHBONE read compares
 
  // Add up errors tha come from WISHBONE read compares
 
  always @u0.cmp_error_detect
 
  always @master.cmp_error_detect
 
    begin
 
    begin
 
      error_count <= error_count + 1;
 
      error_count <= error_count + 1;
 
    end
 
    end
 
 
 
 
 
 
 
  // Define a seperate interface for each PIT instance since each PIT
 
 
 
  // intstance has small differences
 
 
 
  wishbone_if #(.D_WIDTH (16),
 
 
 
                .A_WIDTH (3))
 
 
 
               wb_1(
 
 
 
              .wb_clk   (mstr_test_clk),
 
 
 
              .wb_rst   (1'b0),
 
 
 
              .arst     (rstn));
 
 
 
 
 
 
 
  wishbone_if  wb_2(
 
 
 
              .wb_clk   (mstr_test_clk),
 
 
 
              .wb_rst   (sync_reset),
 
 
 
              .arst     (1'b0));
 
 
 
 
 
 
 
  wishbone_if  wb_3(
 
 
 
              .wb_clk   (mstr_test_clk),
 
 
 
              .wb_rst   (sync_reset),
 
 
 
              .arst     (1'b1));
 
 
 
 
 
 
 
  wishbone_if #(.D_WIDTH (8))
 
 
 
               wb_4(
 
 
 
              .wb_clk   (mstr_test_clk),
 
 
 
              .wb_rst   (sync_reset),
 
 
 
              .arst     (1'b1));
 
 
 
 
 
  // hookup wishbone master model
 
  // hookup wishbone master model
 
  wb_master_model #(.dwidth(16), .awidth(32))
 
  wb_master_model #(.dwidth(16), .awidth(32))
 
          u0 (
 
          master (
 
 
 
          .wb_1(wb_1),
 
 
 
          .wb_2(wb_2),
 
 
 
          .wb_3(wb_3),
 
 
 
          .wb_4(wb_4),
 
          .clk(mstr_test_clk),
 
          .clk(mstr_test_clk),
 
          .rst(rstn),
 
          .rst(rstn),
 
          .adr(adr),
 
          .adr(adr),
 
          .din(dat_i),
 
          .din(dat_i),
 
          .dout(dat_o),
 
          .dout(dat_o),
Line 180... Line 209... 
                 ({16{stb2}} & dat2_i) |
 
                 ({16{stb2}} & dat2_i) |
 
                 ({16{stb3}} & {8'b0, dat3_i[7:0]});
 
                 ({16{stb3}} & {8'b0, dat3_i[7:0]});
 
 
 
 
 
  assign ack = ack_1 || ack_2 || ack_3 || ack_4;
 
  assign ack = ack_1 || ack_2 || ack_3 || ack_4;
 
 
 
 
 
  // hookup wishbone_PIT_master core - Parameters take all default values
 
 
 
 
 
  // hookup wishbone_PIT_slave core - Parameters take all default values
 
  //  Async Reset, 16 bit Bus, 16 bit Granularity,Wait States
 
  //  Async Reset, 16 bit Bus, 16 bit Granularity,Wait States
 
  pit_top #(.SINGLE_CYCLE(1'b0))
 
  pit_top pit_1(
 
          pit_1(
 
 
 
          // wishbone interface
 
          // wishbone interface
 
          .wb_clk_i(mstr_test_clk),
 
          .wb        (wb_1),
 
          .wb_rst_i(1'b0),
 
 
 
          .arst_i(rstn),
 
 
 
          .wb_adr_i(adr[2:0]),
 
 
 
          .wb_dat_i(dat_o),
 
 
 
          .wb_dat_o(dat0_i),
 
          .wb_dat_o(dat0_i),
 
          .wb_we_i(we),
 
          .wb_stb    (stb0),
 
          .wb_stb_i(stb0),
 
          .wb_ack    (ack_1),
 
          .wb_cyc_i(cyc),
 
 
 
          .wb_sel_i( 2'b11 ),
 
 
 
          .wb_ack_o(ack_1),
 
 
 
          .pit_irq_o(inta_1),
 
 
 
 
 
 
 
 
 
          .pit_irq_o (inta_1),
 
          .pit_o(pit_1_out),
 
          .pit_o(pit_1_out),
 
          .ext_sync_i(1'b0),
 
          .ext_sync_i(1'b0),
 
          .cnt_sync_o(count_en_1),
 
          .cnt_sync_o(count_en_1),
 
          .cnt_flag_o(count_flag_1)
 
          .cnt_flag_o(count_flag_1)
 
  );
 
  );
Line 209... Line 231... 
  // hookup wishbone_PIT_slave core - Parameters take all default values
 
  // hookup wishbone_PIT_slave core - Parameters take all default values
 
  //  Sync Reset, 16 bit Bus, 16 bit Granularity
 
  //  Sync Reset, 16 bit Bus, 16 bit Granularity
 
  pit_top #(.ARST_LVL(1'b1))
 
  pit_top #(.ARST_LVL(1'b1))
 
          pit_2(
 
          pit_2(
 
          // wishbone interface
 
          // wishbone interface
 
          .wb_clk_i(mstr_test_clk),
 
          .wb      (wb_2),
 
          .wb_rst_i(sync_reset),
 
 
 
          .arst_i(1'b0),
 
 
 
          .wb_adr_i(adr[2:0]),
 
 
 
          .wb_dat_i(dat_o),
 
 
 
          .wb_dat_o(dat1_i),
 
          .wb_dat_o(dat1_i),
 
          .wb_we_i(we),
 
          .wb_stb  (stb1),
 
          .wb_stb_i(stb1),
 
          .wb_ack  (ack_2),
 
          .wb_cyc_i(cyc),
 
 
 
          .wb_sel_i( 2'b11 ),
 
 
 
          .wb_ack_o(ack_2),
 
 
 
          .pit_irq_o(inta_2),
 
 
 
 
 
 
 
 
 
          .pit_irq_o(inta_2),
 
          .pit_o(pit_2_out),
 
          .pit_o(pit_2_out),
 
          .ext_sync_i(count_en_1),
 
          .ext_sync_i(count_en_1),
 
          .cnt_sync_o(count_en_2),
 
          .cnt_sync_o(count_en_2),
 
          .cnt_flag_o(count_flag_2)
 
          .cnt_flag_o(count_flag_2)
 
  );
 
  );
Line 233... Line 248... 
  // hookup wishbone_PIT_slave core
 
  // hookup wishbone_PIT_slave core
 
  //  16 bit Bus, 16 bit Granularity
 
  //  16 bit Bus, 16 bit Granularity
 
  pit_top #(.NO_PRESCALE(1'b1))
 
  pit_top #(.NO_PRESCALE(1'b1))
 
          pit_3(
 
          pit_3(
 
          // wishbone interface
 
          // wishbone interface
 
          .wb_clk_i(mstr_test_clk),
 
          .wb      (wb_3),
 
          .wb_rst_i(sync_reset),
 
 
 
          .arst_i(1'b1),
 
 
 
          .wb_adr_i(adr[2:0]),
 
 
 
          .wb_dat_i(dat_o),
 
 
 
          .wb_dat_o(dat2_i),
 
          .wb_dat_o(dat2_i),
 
          .wb_we_i(we),
 
          .wb_stb  (stb2),
 
          .wb_stb_i(stb2),
 
          .wb_ack  (ack_3),
 
          .wb_cyc_i(cyc),
 
 
 
          .wb_sel_i( 2'b11 ),
 
 
 
          .wb_ack_o(ack_3),
 
 
 
          .pit_irq_o(inta_3),
 
 
 
 
 
 
 
 
 
          .pit_irq_o(inta_3),
 
          .pit_o(pit_3_out),
 
          .pit_o(pit_3_out),
 
          .ext_sync_i(count_en_1),
 
          .ext_sync_i(count_en_1),
 
          .cnt_sync_o(count_en_3),
 
          .cnt_sync_o(count_en_3),
 
          .cnt_flag_o(count_flag_3)
 
          .cnt_flag_o(count_flag_3)
 
  );
 
  );
 
 
 
 
 
  // hookup wishbone_PIT_slave core
 
  // hookup wishbone_PIT_slave core
 
  //  8 bit Bus, 8 bit Granularity
 
  //  8 bit Bus, 8 bit Granularity
 
  pit_top #(.DWIDTH(8))
 
  pit_top #(.D_WIDTH(8))
 
          pit_4(
 
          pit_4(
 
          // wishbone interface
 
          // wishbone interface
 
          .wb_clk_i(mstr_test_clk),
 
          .wb      (wb_4),
 
          .wb_rst_i(sync_reset),
 
 
 
          .arst_i(1'b1),
 
 
 
          .wb_adr_i(adr[2:0]),
 
 
 
          .wb_dat_i(dat_o[7:0]),
 
 
 
          .wb_dat_o(dat3_i[7:0]),
 
          .wb_dat_o(dat3_i[7:0]),
 
          .wb_we_i(we),
 
          .wb_stb  (stb3),
 
          .wb_stb_i(stb3),
 
          .wb_ack  (ack_4),
 
          .wb_cyc_i(cyc),
 
 
 
          .wb_sel_i( 2'b11 ),
 
 
 
          .wb_ack_o(ack_4),
 
 
 
          .pit_irq_o(inta_4),
 
 
 
 
 
 
 
 
 
          .pit_irq_o(inta_4),
 
          .pit_o(pit_4_out),
 
          .pit_o(pit_4_out),
 
          .ext_sync_i(count_en_1),
 
          .ext_sync_i(count_en_1),
 
          .cnt_sync_o(count_en_4),
 
          .cnt_sync_o(count_en_4),
 
          .cnt_flag_o(count_flag_4)
 
          .cnt_flag_o(count_flag_4)
 
  );
 
  );
 
 
 
 
 
// Test Program
 
// Main Test Program -----------------------------------------------------------
 
initial
 
initial
 
  begin
 
  begin
 
      $display("\nstatus: %t Testbench started", $time);
 
      $display("\nstatus: %t Testbench started", $time);
 
 
 
 
 
      // reset system
 
      // reset system
Line 305... Line 306... 
 
 
 
 
      reg_test_16;
 
      reg_test_16;
 
 
 
 
 
      reg_test_8;
 
      reg_test_8;
 
 
 
 
 
      u0.wb_write(1, SLAVE_0_CNTRL,   PIT_CNTRL_SLAVE); // Enable Slave Mode
 
      master.wb_write(1, SLAVE_0_CNTRL,   PIT_CNTRL_SLAVE); // Enable Slave Mode
 
      u0.wb_write(1, SLAVE_1_CNTRL,   PIT_CNTRL_SLAVE); // Enable Slave Mode
 
      master.wb_write(1, SLAVE_1_CNTRL,   PIT_CNTRL_SLAVE); // Enable Slave Mode
 
      u0.wb_write(1, SLAVE_2_CNTRL_1, 16'h0080); // Enable Slave Mode
 
      master.wb_write(1, SLAVE_2_CNTRL_1, 16'h0080); // Enable Slave Mode
 
      u0.wb_write(1, SLAVE_0_MOD,     16'h000a); // load Modulo
 
      master.wb_write(1, SLAVE_0_MOD,     16'h000a); // load Modulo
 
      u0.wb_write(1, SLAVE_1_MOD,     16'h0010); // load Modulo
 
      master.wb_write(1, SLAVE_1_MOD,     16'h0010); // load Modulo
 
      u0.wb_write(1, SLAVE_2_MOD_0,   16'h0010); // load Modulo
 
      master.wb_write(1, SLAVE_2_MOD_0,   16'h0010); // load Modulo
 
 
 
 
 
      // Set Master Mode PS=0, Modulo=16
 
      // Set Master Mode PS=0, Modulo=16
 
      test_num = test_num + 1;
 
      test_num = test_num + 1;
 
      $display("TEST #%d Starts at vector=%d, ms_test", test_num, vector);
 
      $display("TEST #%d Starts at vector=%d, ms_test", test_num, vector);
 
 
 
 
 
      u0.wb_write(1, PIT_MOD,   16'h0010); // load prescaler hi-byte
 
      master.wb_write(1, PIT_MOD,   16'h0010); // load prescaler hi-byte
 
      u0.wb_write(1, PIT_CNTRL, PIT_CNTRL_ENA); // Enable to start counting
 
      master.wb_write(1, PIT_CNTRL, PIT_CNTRL_ENA); // Enable to start counting
 
      $display("status: %t programmed registers", $time);
 
      $display("status: %t programmed registers", $time);
 
 
 
 
 
      wait_flag_set;  // Wait for Counter to tomeout
 
      wait_flag_set;  // Wait for Counter to tomeout
 
      u0.wb_write(1, PIT_CNTRL, PIT_CNTRL_FLAG | PIT_CNTRL_ENA); //
 
      master.wb_write(1, PIT_CNTRL, PIT_CNTRL_FLAG | PIT_CNTRL_ENA); //
 
 
 
 
 
      wait_flag_set;  // Wait for Counter to tomeout
 
      wait_flag_set;  // Wait for Counter to tomeout
 
      u0.wb_write(1, PIT_CNTRL, PIT_CNTRL_FLAG | PIT_CNTRL_ENA); //
 
      master.wb_write(1, PIT_CNTRL, PIT_CNTRL_FLAG | PIT_CNTRL_ENA); //
 
 
 
 
 
      repeat(10) @(posedge mstr_test_clk);
 
      repeat(10) @(posedge mstr_test_clk);
 
      u0.wb_write(1, PIT_CNTRL, 16'b0); //
 
      master.wb_write(1, PIT_CNTRL, 16'b0); //
 
 
 
 
 
      repeat(10) @(posedge mstr_test_clk);
 
      repeat(10) @(posedge mstr_test_clk);
 
 
 
 
 
      mstr_psx_modx(2,4);
 
      mstr_psx_modx(2,4);
 
 
 
 
Line 339... Line 340... 
 
 
 
 
      repeat(100) @(posedge mstr_test_clk);
 
      repeat(100) @(posedge mstr_test_clk);
 
 
 
 
 
      wrap_up;
 
      wrap_up;
 
 
 
 
 
  end  // Main Test Flow
 
  end  // Main Test Flow  ------------------------------------------------------
 
 
 
 
 
// Poll for flag set
 
// Poll for flag set
 
task wait_flag_set;
 
task wait_flag_set;
 
  u0.wb_read(1, PIT_CNTRL, q);
 
  master.wb_read(1, PIT_CNTRL, q);
 
  while(~|(q & PIT_CNTRL_FLAG))
 
  while(~|(q & PIT_CNTRL_FLAG))
 
    u0.wb_read(1, PIT_CNTRL, q); // poll it until it is set
 
    master.wb_read(1, PIT_CNTRL, q); // poll it until it is set
 
  $display("PIT Flag set detected at vector =%d", vector);
 
  $display("PIT Flag set detected at vector =%d", vector);
 
endtask
 
endtask
 
 
 
 
 
// check register bits - reset, read/write
 
// check register bits - reset, read/write
 
task reg_test_16;
 
task reg_test_16;
 
  test_num = test_num + 1;
 
  test_num = test_num + 1;
 
  $display("TEST #%d Starts at vector=%d, reg_test_16", test_num, vector);
 
  $display("TEST #%d Starts at vector=%d, reg_test_16", test_num, vector);
 
  u0.wb_cmp(0, PIT_CNTRL, 16'h4000);   // verify reset
 
  master.wb_cmp(0, PIT_CNTRL, 16'h4000);   // verify reset
 
  u0.wb_cmp(0, PIT_MOD,   16'h0000);   // verify reset
 
  master.wb_cmp(0, PIT_MOD,   16'h0000);   // verify reset
 
  u0.wb_cmp(0, PIT_COUNT, 16'h0001);   // verify reset
 
  master.wb_cmp(0, PIT_COUNT, 16'h0001);   // verify reset
 
 
 
 
 
  u0.wb_write(1, PIT_CNTRL, 16'hfffe); // load prescaler lo-byte
 
  master.wb_write(1, PIT_CNTRL, 16'hfffe); // load prescaler lo-byte
 
  u0.wb_cmp(  0, PIT_CNTRL, 16'hCf02); // verify write data
 
  master.wb_cmp(  0, PIT_CNTRL, 16'hCf02); // verify write data
 
  u0.wb_write(1, PIT_CNTRL, 16'h0000); // load prescaler lo-byte
 
  master.wb_write(1, PIT_CNTRL, 16'h0000); // load prescaler lo-byte
 
  u0.wb_cmp(  0, PIT_CNTRL, 16'h4000); // verify write data
 
  master.wb_cmp(  0, PIT_CNTRL, 16'h4000); // verify write data
 
 
 
 
 
  u0.wb_write(1, PIT_MOD, 16'h5555); // load prescaler lo-byte
 
  master.wb_write(1, PIT_MOD, 16'h5555); // load prescaler lo-byte
 
  u0.wb_cmp(  0, PIT_MOD, 16'h5555); // verify write data
 
  master.wb_cmp(  0, PIT_MOD, 16'h5555); // verify write data
 
  u0.wb_write(1, PIT_MOD, 16'haaaa); // load prescaler lo-byte
 
  master.wb_write(1, PIT_MOD, 16'haaaa); // load prescaler lo-byte
 
  u0.wb_cmp(  0, PIT_MOD, 16'haaaa); // verify write data
 
  master.wb_cmp(  0, PIT_MOD, 16'haaaa); // verify write data
 
 
 
 
 
  u0.wb_write(0, PIT_COUNT, 16'hfffe);
 
  master.wb_write(0, PIT_COUNT, 16'hfffe);
 
  u0.wb_cmp(  0, PIT_COUNT, 16'h0001); // verify register not writable
 
  master.wb_cmp(  0, PIT_COUNT, 16'h0001); // verify register not writable
 
endtask
 
endtask
 
 
 
 
 
 
 
// Check the registers when the PIT is configured for 8-bit mode
 
task reg_test_8;
 
task reg_test_8;
 
  test_num = test_num + 1;
 
  test_num = test_num + 1;
 
  $display("TEST #%d Starts at vector=%d, reg_test_8", test_num, vector);
 
  $display("TEST #%d Starts at vector=%d, reg_test_8", test_num, vector);
 
  u0.wb_cmp(0, SLAVE_2_CNTRL_0, 16'h0000);   // verify reset
 
  master.wb_cmp(0, SLAVE_2_CNTRL_0, 16'h0000);   // verify reset
 
  u0.wb_cmp(0, SLAVE_2_CNTRL_1, 16'h0040);   // verify reset
 
  master.wb_cmp(0, SLAVE_2_CNTRL_1, 16'h0040);   // verify reset
 
  u0.wb_cmp(0, SLAVE_2_MOD_0,   16'h0000);   // verify reset
 
  master.wb_cmp(0, SLAVE_2_MOD_0,   16'h0000);   // verify reset
 
  u0.wb_cmp(0, SLAVE_2_MOD_1,   16'h0000);   // verify reset
 
  master.wb_cmp(0, SLAVE_2_MOD_1,   16'h0000);   // verify reset
 
  u0.wb_cmp(0, SLAVE_2_COUNT_0, 16'h0001);   // verify reset
 
  master.wb_cmp(0, SLAVE_2_COUNT_0, 16'h0001);   // verify reset
 
  u0.wb_cmp(0, SLAVE_2_COUNT_1, 16'h0000);   // verify reset
 
  master.wb_cmp(0, SLAVE_2_COUNT_1, 16'h0000);   // verify reset
 
 
 
 
 
  u0.wb_write(1, SLAVE_2_CNTRL_0, 16'hfffe); // load prescaler lo-byte
 
  master.wb_write(1, SLAVE_2_CNTRL_0, 16'hfffe); // load prescaler lo-byte
 
  u0.wb_cmp(  0, SLAVE_2_CNTRL_0, 16'h0002); // verify write data
 
  master.wb_cmp(  0, SLAVE_2_CNTRL_0, 16'h0002); // verify write data
 
  u0.wb_write(1, SLAVE_2_CNTRL_0, 16'h0000); // load prescaler lo-byte
 
  master.wb_write(1, SLAVE_2_CNTRL_0, 16'h0000); // load prescaler lo-byte
 
  u0.wb_cmp(  0, SLAVE_2_CNTRL_0, 16'h0000); // verify write data
 
  master.wb_cmp(  0, SLAVE_2_CNTRL_0, 16'h0000); // verify write data
 
  u0.wb_cmp(  0, SLAVE_2_CNTRL_1, 16'h0040); // verify write data
 
  master.wb_cmp(  0, SLAVE_2_CNTRL_1, 16'h0040); // verify write data
 
 
 
 
 
  u0.wb_write(1, SLAVE_2_MOD_0, 16'hff55); // load prescaler lo-byte
 
  master.wb_write(1, SLAVE_2_MOD_0, 16'hff55); // load prescaler lo-byte
 
  u0.wb_cmp(  0, SLAVE_2_MOD_0, 16'h0055); // verify write data
 
  master.wb_cmp(  0, SLAVE_2_MOD_0, 16'h0055); // verify write data
 
  u0.wb_write(1, SLAVE_2_MOD_0, 16'hffaa); // load prescaler lo-byte
 
  master.wb_write(1, SLAVE_2_MOD_0, 16'hffaa); // load prescaler lo-byte
 
  u0.wb_cmp(  0, SLAVE_2_MOD_0, 16'h00aa); // verify write data
 
  master.wb_cmp(  0, SLAVE_2_MOD_0, 16'h00aa); // verify write data
 
  u0.wb_write(1, SLAVE_2_MOD_1, 16'hff66); // load prescaler lo-byte
 
  master.wb_write(1, SLAVE_2_MOD_1, 16'hff66); // load prescaler lo-byte
 
  u0.wb_cmp(  0, SLAVE_2_MOD_1, 16'h0066); // verify write data
 
  master.wb_cmp(  0, SLAVE_2_MOD_1, 16'h0066); // verify write data
 
  u0.wb_write(1, SLAVE_2_MOD_1, 16'hff99); // load prescaler lo-byte
 
  master.wb_write(1, SLAVE_2_MOD_1, 16'hff99); // load prescaler lo-byte
 
  u0.wb_cmp(  0, SLAVE_2_MOD_1, 16'h0099); // verify write data
 
  master.wb_cmp(  0, SLAVE_2_MOD_1, 16'h0099); // verify write data
 
  u0.wb_write(1, SLAVE_2_MOD_1, 16'hff00); // load prescaler lo-byte
 
  master.wb_write(1, SLAVE_2_MOD_1, 16'hff00); // load prescaler lo-byte
 
 
 
 
 
  u0.wb_write(0, SLAVE_2_COUNT_0, 16'hfffe);
 
  master.wb_write(0, SLAVE_2_COUNT_0, 16'hfffe);
 
  u0.wb_cmp(  0, SLAVE_2_COUNT_0, 16'h0001); // verify register not writable
 
  master.wb_cmp(  0, SLAVE_2_COUNT_0, 16'h0001); // verify register not writable
 
  u0.wb_write(0, SLAVE_2_COUNT_1, 16'hfffe);
 
  master.wb_write(0, SLAVE_2_COUNT_1, 16'hfffe);
 
  u0.wb_cmp(  0, SLAVE_2_COUNT_1, 16'h0000); // verify register not writable
 
  master.wb_cmp(  0, SLAVE_2_COUNT_1, 16'h0000); // verify register not writable
 
endtask
 
endtask
 
 
 
 
 
task mstr_psx_modx(
 
task mstr_psx_modx(
 
  logic [ 3:0] ps_val,
 
  logic [ 3:0] ps_val,
 
  logic [15:0] mod_val);
 
  logic [15:0] mod_val);
Line 413... Line 415... 
  $display("TEST #%d Starts at vector=%d, mstr_psx_modx Pre=%h, Mod=%h",
 
  $display("TEST #%d Starts at vector=%d, mstr_psx_modx Pre=%h, Mod=%h",
 
          test_num, vector, ps_val, mod_val);
 
          test_num, vector, ps_val, mod_val);
 
  // program internal registers
 
  // program internal registers
 
 
 
 
 
  cntrl_val = {1'b0, 3'b0, ps_val, 8'b0} | PIT_CNTRL_IRQEN;
 
  cntrl_val = {1'b0, 3'b0, ps_val, 8'b0} | PIT_CNTRL_IRQEN;
 
  u0.wb_write(1, PIT_MOD,   mod_val); // load modulo
 
  master.wb_write(1, PIT_MOD,   mod_val); // load modulo
 
  u0.wb_write(1, PIT_CNTRL, ( cntrl_val | PIT_CNTRL_ENA)); // Enable to start counting
 
  master.wb_write(1, PIT_CNTRL, ( cntrl_val | PIT_CNTRL_ENA)); // Enable to start counting
 
 
 
 
 
  wait_flag_set;  // Wait for Counter to timeout
 
  wait_flag_set;  // Wait for Counter to timeout
 
  u0.wb_write(1, PIT_CNTRL, cntrl_val | PIT_CNTRL_FLAG | PIT_CNTRL_ENA); //
 
  master.wb_write(1, PIT_CNTRL, cntrl_val | PIT_CNTRL_FLAG | PIT_CNTRL_ENA); //
 
 
 
 
 
  wait_flag_set;  // Wait for Counter to timeout
 
  wait_flag_set;  // Wait for Counter to timeout
 
  u0.wb_write(1, PIT_CNTRL, cntrl_val | PIT_CNTRL_FLAG | PIT_CNTRL_ENA); //
 
  master.wb_write(1, PIT_CNTRL, cntrl_val | PIT_CNTRL_FLAG | PIT_CNTRL_ENA); //
 
 
 
 
 
  repeat(10) @(posedge mstr_test_clk);
 
  repeat(10) @(posedge mstr_test_clk);
 
 
 
 
 
  u0.wb_write(1, PIT_CNTRL, 16'b0); //
 
  master.wb_write(1, PIT_CNTRL, 16'b0); //
 
endtask
 
endtask
 
 
 
 
 
 
 
// End the simulation and print out the final results
 
task wrap_up;
 
task wrap_up;
 
  test_num = test_num + 1;
 
  test_num = test_num + 1;
 
  repeat(10) @(posedge mstr_test_clk);
 
  repeat(10) @(posedge mstr_test_clk);
 
  $display("\nSimulation Finished!! - vector =%d", vector);
 
  $display("\nSimulation Finished!! - vector =%d", vector);
 
  if (error_count == 0)
 
  if (error_count == 0)

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