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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// 45678901234567890123456789012345678901234567890123456789012345678901234567890
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// 45678901234567890123456789012345678901234567890123456789012345678901234567890
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module pit_top #(parameter ARST_LVL = 1'b0, // asynchronous reset level
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module pit_top #(parameter D_WIDTH = 16,
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parameter ARST_LVL = 1'b0, // asynchronous reset level
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parameter SINGLE_CYCLE = 1'b0, // Add a wait state to bus transcation
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parameter PRE_COUNT_SIZE = 15, // Prescale Counter size
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parameter PRE_COUNT_SIZE = 15, // Prescale Counter size
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parameter COUNT_SIZE = 16, // Main counter size
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parameter COUNT_SIZE = 16, // Main counter size
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parameter DECADE_CNTR = 1'b1, // Prescale rollover decode
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parameter DECADE_CNTR = 1'b1, // Prescale rollover decode
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parameter NO_PRESCALE = 1'b0, // Remove prescale function
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parameter NO_PRESCALE = 1'b0) // Remove prescale function
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parameter SINGLE_CYCLE = 1'b0, // No bus wait state added
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parameter DWIDTH = 16) // Data bus width
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(
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(
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// Wishbone Signals
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// Wishbone Signals
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output [DWIDTH-1:0] wb_dat_o, // databus output
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wishbone_if.slave wb, // Wishbone interface instance
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output wb_ack_o, // bus cycle acknowledge output
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output logic [D_WIDTH-1:0] wb_dat_o, // databus output - Pseudo Register
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input wb_clk_i, // master clock input
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output logic wb_ack, // bus cycle acknowledge output
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input wb_rst_i, // synchronous active high reset
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input logic wb_stb, // stobe/core select signal
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input arst_i, // asynchronous reset
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input [2:0] wb_adr_i, // lower address bits
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input [DWIDTH-1:0] wb_dat_i, // databus input
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input wb_we_i, // write enable input
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input wb_stb_i, // stobe/core select signal
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input wb_cyc_i, // valid bus cycle input
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input [1:0] wb_sel_i, // Select byte in word bus transaction
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// PIT IO Signals
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// PIT IO Signals
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output pit_o, // PIT output pulse
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output pit_o, // PIT output pulse
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output pit_irq_o, // PIT interrupt request signal output
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output pit_irq_o, // PIT interrupt request signal output
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output cnt_flag_o, // PIT Flag Out
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output cnt_flag_o, // PIT Flag Out
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output cnt_sync_o, // PIT Master Enable for Slave PIT's
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output cnt_sync_o, // PIT Master Enable for Slave PIT's
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logic counter_sync; //
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logic counter_sync; //
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logic pit_flag; //
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logic pit_flag; //
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// Wishbone Bus interface
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// Wishbone Bus interface
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pit_wb_bus #(.ARST_LVL(ARST_LVL),
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pit_wb_bus #(.ARST_LVL(ARST_LVL),
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.SINGLE_CYCLE(SINGLE_CYCLE),
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.D_WIDTH (D_WIDTH))
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.DWIDTH(DWIDTH))
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wishbone(
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wishbone(
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// Wishbone Signals
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.wb ( wb ),
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.wb_stb ( wb_stb ),
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.wb_ack ( wb_ack ),
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.irq_source ( cnt_flag_o ),
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.irq_source ( cnt_flag_o ),
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.read_regs ( // in -- status register bits
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.read_regs ( // in -- status register bits
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{ cnt_n,
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{ cnt_n,
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mod_value,
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mod_value,
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{pit_slave, DECADE_CNTR, NO_PRESCALE, 1'b0, pit_pre_scl,
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{pit_slave, DECADE_CNTR, NO_PRESCALE, 1'b0, pit_pre_scl,
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}
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}
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),
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),
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.*);
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.*);
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// -----------------------------------------------------------------------------
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// -----------------------------------------------------------------------------
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pit_regs #(.ARST_LVL(ARST_LVL),
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pit_regs #(.COUNT_SIZE(COUNT_SIZE),
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.COUNT_SIZE(COUNT_SIZE),
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.NO_PRESCALE(NO_PRESCALE),
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.NO_PRESCALE(NO_PRESCALE),
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.DWIDTH(DWIDTH))
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.D_WIDTH(D_WIDTH))
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regs(
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regs(
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.bus_clk ( wb_clk_i ),
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.bus_clk ( wb.wb_clk ),
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.write_bus ( wb_dat_i ),
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.write_bus ( wb.wb_dat ),
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.*);
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.*);
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// -----------------------------------------------------------------------------
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// -----------------------------------------------------------------------------
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pit_prescale #(.COUNT_SIZE(PRE_COUNT_SIZE),
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pit_prescale #(.COUNT_SIZE(PRE_COUNT_SIZE),
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.DECADE_CNTR(DECADE_CNTR),
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.DECADE_CNTR(DECADE_CNTR),
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.NO_PRESCALE(NO_PRESCALE))
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.NO_PRESCALE(NO_PRESCALE))
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prescale(
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prescale(
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.bus_clk ( wb_clk_i ),
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.bus_clk ( wb.wb_clk ),
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.divisor ( pit_pre_scl ),
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.divisor ( pit_pre_scl ),
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.*);
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.*);
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// -----------------------------------------------------------------------------
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// -----------------------------------------------------------------------------
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pit_count #(.COUNT_SIZE(COUNT_SIZE))
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pit_count #(.COUNT_SIZE(COUNT_SIZE))
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counter(
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counter(
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.bus_clk ( wb_clk_i ),
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.bus_clk ( wb.wb_clk ),
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.*);
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.*);
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endmodule // pit_top
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endmodule // pit_top
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