-----------------------------------------------------------------------
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-----------------------------------------------------------------------
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---- ----
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---- ----
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---- Present - a lightweight block cipher project ----
|
---- Present - a lightweight block cipher project ----
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---- ----
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---- ----
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---- This file is part of the Present - a lightweight block ----
|
---- This file is part of the Present - a lightweight block ----
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---- cipher project ----
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---- cipher project ----
|
---- http://www.http://opencores.org/project,present ----
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---- http://www.http://opencores.org/project,present ----
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---- ----
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---- ----
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---- Description: ----
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---- Description: ----
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---- Shift register with parallel input/output. Nothing special----
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---- Shift register with parallel input/output. Nothing special----
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---- except configuration - it enables wider input than output and ----
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---- except configuration - it enables wider input than output and ----
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---- inverse config. ----
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---- inverse config. ----
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---- To Do: ----
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---- To Do: ----
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---- ----
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---- ----
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---- Author(s): ----
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---- Author(s): ----
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---- - Krzysztof Gajewski, gajos@opencores.org ----
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---- - Krzysztof Gajewski, gajos@opencores.org ----
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---- k.gajewski@gmail.com ----
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---- k.gajewski@gmail.com ----
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---- ----
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---- ----
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-----------------------------------------------------------------------
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-----------------------------------------------------------------------
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---- ----
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---- ----
|
---- Copyright (C) 2013 Authors and OPENCORES.ORG ----
|
---- Copyright (C) 2013 Authors and OPENCORES.ORG ----
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---- ----
|
---- ----
|
---- This source file may be used and distributed without ----
|
---- This source file may be used and distributed without ----
|
---- restriction provided that this copyright statement is not ----
|
---- restriction provided that this copyright statement is not ----
|
---- removed from the file and that any derivative work contains ----
|
---- removed from the file and that any derivative work contains ----
|
---- the original copyright notice and the associated disclaimer. ----
|
---- the original copyright notice and the associated disclaimer. ----
|
---- ----
|
---- ----
|
---- This source file is free software; you can redistribute it ----
|
---- This source file is free software; you can redistribute it ----
|
---- and-or modify it under the terms of the GNU Lesser General ----
|
---- and-or modify it under the terms of the GNU Lesser General ----
|
---- Public License as published by the Free Software Foundation; ----
|
---- Public License as published by the Free Software Foundation; ----
|
---- either version 2.1 of the License, or (at your option) any ----
|
---- either version 2.1 of the License, or (at your option) any ----
|
---- later version. ----
|
---- later version. ----
|
---- ----
|
---- ----
|
---- This source is distributed in the hope that it will be ----
|
---- This source is distributed in the hope that it will be ----
|
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
|
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
|
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
|
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
|
---- PURPOSE. See the GNU Lesser General Public License for more ----
|
---- PURPOSE. See the GNU Lesser General Public License for more ----
|
---- details. ----
|
---- details. ----
|
---- ----
|
---- ----
|
---- You should have received a copy of the GNU Lesser General ----
|
---- You should have received a copy of the GNU Lesser General ----
|
---- Public License along with this source; if not, download it ----
|
---- Public License along with this source; if not, download it ----
|
---- from http://www.opencores.org/lgpl.shtml ----
|
---- from http://www.opencores.org/lgpl.shtml ----
|
---- ----
|
---- ----
|
-----------------------------------------------------------------------
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-----------------------------------------------------------------------
|
library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
|
|
|
-- Uncomment the following library declaration if using
|
-- Uncomment the following library declaration if using
|
-- arithmetic functions with Signed or Unsigned values
|
-- arithmetic functions with Signed or Unsigned values
|
--use IEEE.NUMERIC_STD.ALL;
|
--use IEEE.NUMERIC_STD.ALL;
|
|
|
-- Uncomment the following library declaration if instantiating
|
-- Uncomment the following library declaration if instantiating
|
-- any Xilinx primitives in this code.
|
-- any Xilinx primitives in this code.
|
--library UNISIM;
|
--library UNISIM;
|
--use UNISIM.VComponents.all;
|
--use UNISIM.VComponents.all;
|
|
|
entity ShiftReg is
|
entity ShiftReg is
|
generic (
|
generic (
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length_1 : integer := 8;
|
length_1 : integer := 8;
|
length_2 : integer := 64;
|
length_2 : integer := 64;
|
internal_data : integer := 64
|
internal_data : integer := 64
|
);
|
);
|
port (
|
port (
|
input : in STD_LOGIC_VECTOR(length_1 - 1 downto 0);
|
input : in STD_LOGIC_VECTOR(length_1 - 1 downto 0);
|
output : out STD_LOGIC_VECTOR(length_2 - 1 downto 0);
|
output : out STD_LOGIC_VECTOR(length_2 - 1 downto 0);
|
en : in STD_LOGIC;
|
en : in STD_LOGIC;
|
shift : in STD_LOGIC;
|
shift : in STD_LOGIC;
|
clk : in STD_LOGIC;
|
clk : in STD_LOGIC;
|
reset : in STD_LOGIC
|
reset : in STD_LOGIC
|
);
|
);
|
end ShiftReg;
|
end ShiftReg;
|
|
|
architecture Behavioral of ShiftReg is
|
architecture Behavioral of ShiftReg is
|
|
|
signal data : STD_LOGIC_VECTOR(internal_data - 1 downto 0);
|
signal data : STD_LOGIC_VECTOR(internal_data - 1 downto 0);
|
|
|
begin
|
begin
|
reg : process (clk, reset, data)
|
reg : process (clk, reset, data)
|
begin
|
begin
|
if (clk'event and clk = '1') then
|
|
if (reset = '1') then
|
if (reset = '1') then
|
data <= (others => '0');
|
data <= (others => '0');
|
elsif (en = '1') then
|
elsif (clk'event and clk = '1') then
|
|
if (en = '1') then
|
data(internal_data - 1 downto internal_data - length_1) <= input;
|
data(internal_data - 1 downto internal_data - length_1) <= input;
|
else
|
else
|
if (shift = '1') then
|
if (shift = '1') then
|
data <= '0' & data(internal_data - 1 downto 1);
|
data <= '0' & data(internal_data - 1 downto 1);
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
output <= data(length_2 - 1 downto 0);
|
output <= data(length_2 - 1 downto 0);
|
end process reg;
|
end process reg;
|
|
|
end Behavioral;
|
end Behavioral;
|
|
|
|
|
