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https://opencores.org/ocsvn/ram_wb/ram_wb/trunk
[/] [ram_wb/] [trunk/] [rtl/] [verilog/] [ram_wb.v] - Diff between revs 5 and 8
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| Rev 5 |
Rev 8 |
| Line 29... |
Line 29... |
assign wr_data[ 7: 0] = sel_i[0] ? dat_i[ 7: 0] : dat_o[ 7: 0];
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assign wr_data[ 7: 0] = sel_i[0] ? dat_i[ 7: 0] : dat_o[ 7: 0];
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ram
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ram
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#
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#
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(
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(
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.DATA_WIDTH(dat_width),
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.dat_width(dat_width),
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.ADDR_WIDTH(adr_width),
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.adr_width(adr_width),
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.MEM_SIZE(mem_size)
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.mem_size(mem_size)
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)
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)
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ram0
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ram0
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(
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(
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.dat_i(wr_data),
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.dat_i(wr_data),
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.dat_o(dat_o),
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.dat_o(dat_o),
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