2) Load the password byte-by-byte into the password_input port. The lenght of the password is KEY_SIZE
2) Load the password byte-by-byte into the password_input port. The lenght of the password is KEY_SIZE
3) Issue 768 clocks to perform key expansion
3) Issue 768 clocks to perform key expansion
4) Wait about 1000 clocks while the module discards the first 1000 weak bytes of the stream.
4) Wait 1536 clocks while the module discards the first weak bytes of the stream as per RFC 4345.
5) Now you should start receiving the pseudo-random stream via the output bus, one byte every clock. The output_ready signal signals when a valid byte is present at the output K.
5) Now you should start receiving the pseudo-random stream via the output bus, one byte every clock. The output_ready signal signals when a valid byte is present at the output K.
To encrypt or decrypt using RC4 you simply xor your data with the output stream.
To encrypt or decrypt using RC4 you simply xor your data with the output stream.
The testbench and makefile work using icarus verilog and you can peer into rc4_tb.v to see an example implementation.
The testbench and makefile work using icarus verilog and you can peer into rc4_tb.v to see an example implementation.
