| Line 7... |
Line 7... |
--
|
--
|
-- Description
|
-- Description
|
-- Contains a platform to build endpoints on.
|
-- Contains a platform to build endpoints on.
|
--
|
--
|
-- To Do:
|
-- To Do:
|
-- -
|
-- REMARK: Clean up and increase the speed of the interface to packet handlers.
|
|
-- REMARK: 8-bit deviceId has not been verified, fix.
|
|
-- REMARK: Egress; Places packets in different queues depending on the packet priority?
|
|
-- REMARK: Add verification of all sizes of packets.
|
--
|
--
|
-- Author(s):
|
-- Author(s):
|
-- - Magnus Rosenius, magro732@opencores.org
|
-- - Magnus Rosenius, magro732@opencores.org
|
--
|
--
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
| Line 54... |
Line 57... |
-- * Adds in-the-middle and trailing CRC.
|
-- * Adds in-the-middle and trailing CRC.
|
-- * Receives packets from logical-layer handlers.
|
-- * Receives packets from logical-layer handlers.
|
-- * Receives header and deviceIDs in seperate accesses to facilitate 8- and
|
-- * Receives header and deviceIDs in seperate accesses to facilitate 8- and
|
-- 16-bit deviceAddress support. All fields are right-justified.
|
-- 16-bit deviceAddress support. All fields are right-justified.
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- REMARK: Egress; Places packets in different queues depending on the packet priority?
|
|
-- REMARK: Do not use Wishbone, use request/grant scheme instead?
|
|
-- REMARK: 8-bit deviceId has not been verified, fix.
|
|
library ieee;
|
library ieee;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
use ieee.numeric_std.all;
|
use ieee.numeric_std.all;
|
use work.rio_common.all;
|
use work.rio_common.all;
|
|
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
--
|
--
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
entity RioLogicalCommon is
|
entity RioLogicalCommon is
|
|
generic(
|
|
PORTS : natural);
|
port(
|
port(
|
clk : in std_logic;
|
clk : in std_logic;
|
areset_n : in std_logic;
|
areset_n : in std_logic;
|
enable : in std_logic;
|
enable : in std_logic;
|
|
|
| Line 84... |
Line 86... |
writeFrame_o : out std_logic;
|
writeFrame_o : out std_logic;
|
writeFrameAbort_o : out std_logic;
|
writeFrameAbort_o : out std_logic;
|
writeContent_o : out std_logic;
|
writeContent_o : out std_logic;
|
writeContentData_o : out std_logic_vector(31 downto 0);
|
writeContentData_o : out std_logic_vector(31 downto 0);
|
|
|
masterCyc_o : out std_logic;
|
inboundCyc_o : out std_logic;
|
masterStb_o : out std_logic;
|
inboundStb_o : out std_logic;
|
masterAdr_o : out std_logic_vector(7 downto 0);
|
inboundAdr_o : out std_logic_vector(7 downto 0);
|
masterDat_o : out std_logic_vector(31 downto 0);
|
inboundDat_o : out std_logic_vector(31 downto 0);
|
masterAck_i : in std_logic;
|
inboundAck_i : in std_logic;
|
|
|
slaveCyc_i : in std_logic;
|
outboundCyc_i : in std_logic_vector(PORTS-1 downto 0);
|
slaveStb_i : in std_logic;
|
outboundStb_i : in std_logic_vector(PORTS-1 downto 0);
|
slaveDat_i : in std_logic_vector(31 downto 0);
|
outboundDat_i : in std_logic_vector(32*PORTS-1 downto 0);
|
slaveAck_o : out std_logic);
|
outboundAck_o : out std_logic_vector(PORTS-1 downto 0));
|
end entity;
|
end entity;
|
|
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
--
|
--
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
architecture RioLogicalCommon of RioLogicalCommon is
|
architecture RioLogicalCommon of RioLogicalCommon is
|
|
|
|
component RioLogicalCommonInterconnect is
|
|
generic(
|
|
WIDTH : natural);
|
|
port(
|
|
clk : in std_logic;
|
|
areset_n : in std_logic;
|
|
|
|
stb_i : in std_logic_vector(WIDTH-1 downto 0);
|
|
dataM_i : in std_logic_vector(32*WIDTH-1 downto 0);
|
|
ack_o : out std_logic_vector(WIDTH-1 downto 0);
|
|
|
|
stb_o : out std_logic;
|
|
dataS_o : out std_logic_vector(31 downto 0);
|
|
ack_i : in std_logic);
|
|
end component;
|
|
|
component RioLogicalCommonIngress is
|
component RioLogicalCommonIngress is
|
port(
|
port(
|
clk : in std_logic;
|
clk : in std_logic;
|
areset_n : in std_logic;
|
areset_n : in std_logic;
|
|
|
| Line 113... |
Line 131... |
readFrame_o : out std_logic;
|
readFrame_o : out std_logic;
|
readContent_o : out std_logic;
|
readContent_o : out std_logic;
|
readContentEnd_i : in std_logic;
|
readContentEnd_i : in std_logic;
|
readContentData_i : in std_logic_vector(31 downto 0);
|
readContentData_i : in std_logic_vector(31 downto 0);
|
|
|
masterCyc_o : out std_logic;
|
inboundCyc_o : out std_logic;
|
masterStb_o : out std_logic;
|
inboundStb_o : out std_logic;
|
masterAdr_o : out std_logic_vector(7 downto 0);
|
inboundAdr_o : out std_logic_vector(7 downto 0);
|
masterDat_o : out std_logic_vector(31 downto 0);
|
inboundDat_o : out std_logic_vector(31 downto 0);
|
masterAck_i : in std_logic);
|
inboundAck_i : in std_logic);
|
end component;
|
end component;
|
|
|
component RioLogicalCommonEgress is
|
component RioLogicalCommonEgress is
|
port(
|
port(
|
clk : in std_logic;
|
clk : in std_logic;
|
| Line 131... |
Line 149... |
writeFrame_o : out std_logic;
|
writeFrame_o : out std_logic;
|
writeFrameAbort_o : out std_logic;
|
writeFrameAbort_o : out std_logic;
|
writeContent_o : out std_logic;
|
writeContent_o : out std_logic;
|
writeContentData_o : out std_logic_vector(31 downto 0);
|
writeContentData_o : out std_logic_vector(31 downto 0);
|
|
|
slaveCyc_i : in std_logic;
|
outboundCyc_i : in std_logic;
|
slaveStb_i : in std_logic;
|
outboundStb_i : in std_logic;
|
slaveDat_i : in std_logic_vector(31 downto 0);
|
outboundDat_i : in std_logic_vector(31 downto 0);
|
slaveAck_o : out std_logic);
|
outboundAck_o : out std_logic);
|
end component;
|
end component;
|
|
|
|
signal outboundStb : std_logic;
|
|
signal outboundDat : std_logic_vector(31 downto 0);
|
|
signal outboundAck : std_logic;
|
|
|
begin
|
begin
|
|
|
Ingress: RioLogicalCommonIngress
|
Ingress: RioLogicalCommonIngress
|
port map(
|
port map(
|
clk=>clk, areset_n=>areset_n,
|
clk=>clk, areset_n=>areset_n,
|
readFrameEmpty_i=>readFrameEmpty_i,
|
readFrameEmpty_i=>readFrameEmpty_i,
|
readFrame_o=>readFrame_o,
|
readFrame_o=>readFrame_o,
|
readContent_o=>readContent_o,
|
readContent_o=>readContent_o,
|
readContentEnd_i=>readContentEnd_i,
|
readContentEnd_i=>readContentEnd_i,
|
readContentData_i=>readContentData_i,
|
readContentData_i=>readContentData_i,
|
masterCyc_o=>masterCyc_o,
|
inboundCyc_o=>inboundCyc_o,
|
masterStb_o=>masterStb_o,
|
inboundStb_o=>inboundStb_o,
|
masterAdr_o=>masterAdr_o,
|
inboundAdr_o=>inboundAdr_o,
|
masterDat_o=>masterDat_o,
|
inboundDat_o=>inboundDat_o,
|
masterAck_i=>masterAck_i);
|
inboundAck_i=>inboundAck_i);
|
|
|
|
EgressInterconnect: RioLogicalCommonInterconnect
|
|
generic map(WIDTH=>PORTS)
|
|
port map(
|
|
clk=>clk, areset_n=>areset_n,
|
|
stb_i=>outboundStb_i,
|
|
dataM_i=>outboundDat_i,
|
|
ack_o=>outboundAck_o,
|
|
stb_o=>outboundStb,
|
|
dataS_o=>outboundDat,
|
|
ack_i=>outboundAck);
|
|
|
Egress: RioLogicalCommonEgress
|
Egress: RioLogicalCommonEgress
|
port map(
|
port map(
|
clk=>clk, areset_n=>areset_n,
|
clk=>clk, areset_n=>areset_n,
|
writeFrameFull_i=>writeFrameFull_i,
|
writeFrameFull_i=>writeFrameFull_i,
|
writeFrame_o=>writeFrame_o,
|
writeFrame_o=>writeFrame_o,
|
writeFrameAbort_o=>writeFrameAbort_o,
|
writeFrameAbort_o=>writeFrameAbort_o,
|
writeContent_o=>writeContent_o,
|
writeContent_o=>writeContent_o,
|
writeContentData_o=>writeContentData_o,
|
writeContentData_o=>writeContentData_o,
|
slaveCyc_i=>slaveCyc_i,
|
outboundCyc_i=>'1',
|
slaveStb_i=>slaveStb_i,
|
outboundStb_i=>outboundStb,
|
slaveDat_i=>slaveDat_i,
|
outboundDat_i=>outboundDat,
|
slaveAck_o=>slaveAck_o);
|
outboundAck_o=>outboundAck);
|
|
|
end architecture;
|
end architecture;
|
|
|
|
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- RioLogicalCommonIngress.
|
-- RioLogicalCommonIngress.
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- REMARK: Check the destination address to see if it matches the one configured???
|
|
-- REMARK: Remove the acknowledge on all accesses on the master bus.
|
|
-- REMARK: Add component declarations to riocommon.vhd.
|
|
library ieee;
|
library ieee;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
use ieee.numeric_std.all;
|
use ieee.numeric_std.all;
|
use work.rio_common.all;
|
use work.rio_common.all;
|
|
|
| Line 195... |
Line 225... |
readFrame_o : out std_logic;
|
readFrame_o : out std_logic;
|
readContent_o : out std_logic;
|
readContent_o : out std_logic;
|
readContentEnd_i : in std_logic;
|
readContentEnd_i : in std_logic;
|
readContentData_i : in std_logic_vector(31 downto 0);
|
readContentData_i : in std_logic_vector(31 downto 0);
|
|
|
masterCyc_o : out std_logic;
|
inboundCyc_o : out std_logic;
|
masterStb_o : out std_logic;
|
inboundStb_o : out std_logic;
|
masterAdr_o : out std_logic_vector(7 downto 0);
|
inboundAdr_o : out std_logic_vector(7 downto 0);
|
masterDat_o : out std_logic_vector(31 downto 0);
|
inboundDat_o : out std_logic_vector(31 downto 0);
|
masterAck_i : in std_logic);
|
inboundAck_i : in std_logic);
|
end entity;
|
end entity;
|
|
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
--
|
--
|
| Line 214... |
Line 244... |
SEND_HEADER, SEND_DESTINATION, SEND_SOURCE,
|
SEND_HEADER, SEND_DESTINATION, SEND_SOURCE,
|
FORWARD_SHORT, FORWARD_CRC, FORWARD_LONG, FORWARD_LAST,
|
FORWARD_SHORT, FORWARD_CRC, FORWARD_LONG, FORWARD_LAST,
|
END_PACKET);
|
END_PACKET);
|
signal state : StateType;
|
signal state : StateType;
|
|
|
signal packetPosition : natural range 0 to 32;
|
signal packetPosition : natural range 0 to 68;
|
signal packetContent : std_logic_vector(63 downto 0);
|
signal packetContent : std_logic_vector(63 downto 0);
|
|
|
signal tt : std_logic_vector(1 downto 0);
|
signal tt : std_logic_vector(1 downto 0);
|
signal ftype : std_logic_vector(3 downto 0);
|
signal ftype : std_logic_vector(3 downto 0);
|
signal transaction : std_logic_vector(3 downto 0);
|
signal transaction : std_logic_vector(3 downto 0);
|
| Line 238... |
Line 268... |
transaction <= "0000";
|
transaction <= "0000";
|
|
|
readContent_o <= '0';
|
readContent_o <= '0';
|
readFrame_o <= '0';
|
readFrame_o <= '0';
|
|
|
masterCyc_o <= '0';
|
inboundCyc_o <= '0';
|
masterStb_o <= '0';
|
inboundStb_o <= '0';
|
masterAdr_o <= (others=>'0');
|
inboundAdr_o <= (others=>'0');
|
masterDat_o <= (others=>'0');
|
inboundDat_o <= (others=>'0');
|
elsif (clk'event and clk = '1') then
|
elsif (clk'event and clk = '1') then
|
readContent_o <= '0';
|
readContent_o <= '0';
|
readFrame_o <= '0';
|
readFrame_o <= '0';
|
|
|
case state is
|
case state is
|
| Line 296... |
Line 326... |
|
|
when SEND_HEADER =>
|
when SEND_HEADER =>
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
--
|
--
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
masterCyc_o <= '1';
|
inboundCyc_o <= '1';
|
masterStb_o <= '1';
|
inboundStb_o <= '1';
|
masterAdr_o <= ftype & transaction;
|
inboundAdr_o <= ftype & transaction;
|
masterDat_o <= x"0000" & packetContent(63 downto 48);
|
inboundDat_o <= x"0000" & packetContent(63 downto 48);
|
packetContent <= packetContent(47 downto 0) & x"0000";
|
packetContent <= packetContent(47 downto 0) & x"0000";
|
|
|
state <= SEND_DESTINATION;
|
state <= SEND_DESTINATION;
|
|
|
when SEND_DESTINATION =>
|
when SEND_DESTINATION =>
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
--
|
--
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
if (masterAck_i = '1') then
|
if (inboundAck_i = '1') then
|
if (tt = "00") then
|
if (tt = "00") then
|
masterDat_o <= x"000000" & packetContent(63 downto 56);
|
inboundDat_o <= x"000000" & packetContent(63 downto 56);
|
packetContent <= packetContent(55 downto 0) & x"00";
|
packetContent <= packetContent(55 downto 0) & x"00";
|
elsif (tt = "01") then
|
elsif (tt = "01") then
|
masterDat_o <= x"0000" & packetContent(63 downto 48);
|
inboundDat_o <= x"0000" & packetContent(63 downto 48);
|
packetContent <= packetContent(47 downto 0) & x"0000";
|
packetContent <= packetContent(47 downto 0) & x"0000";
|
end if;
|
end if;
|
|
|
state <= SEND_SOURCE;
|
state <= SEND_SOURCE;
|
end if;
|
end if;
|
|
|
when SEND_SOURCE =>
|
when SEND_SOURCE =>
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
--
|
--
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
if (masterAck_i = '1') then
|
if (inboundAck_i = '1') then
|
if (tt = "00") then
|
if (tt = "00") then
|
masterDat_o <= x"000000" & packetContent(63 downto 56);
|
inboundDat_o <= x"000000" & packetContent(63 downto 56);
|
packetContent <= packetContent(55 downto 0) & x"00";
|
packetContent <= packetContent(55 downto 0) & x"00";
|
elsif (tt = "01") then
|
elsif (tt = "01") then
|
masterDat_o <= x"0000" & packetContent(63 downto 48);
|
inboundDat_o <= x"0000" & packetContent(63 downto 48);
|
packetContent <= packetContent(47 downto 32) & readContentData_i & x"0000";
|
packetContent <= packetContent(47 downto 32) & readContentData_i & x"0000";
|
readContent_o <= '1';
|
readContent_o <= '1';
|
end if;
|
end if;
|
|
|
state <= FORWARD_SHORT;
|
state <= FORWARD_SHORT;
|
| Line 341... |
Line 371... |
|
|
when FORWARD_SHORT =>
|
when FORWARD_SHORT =>
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
--
|
--
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
if (masterAck_i = '1') then
|
if (inboundAck_i = '1') then
|
packetPosition <= packetPosition + 1;
|
packetPosition <= packetPosition + 1;
|
|
|
if (tt = "00") then
|
if (tt = "00") then
|
masterDat_o <= packetContent(63 downto 32);
|
inboundDat_o <= packetContent(63 downto 32);
|
packetContent <= packetContent(31 downto 0) & readContentData_i;
|
packetContent <= packetContent(31 downto 0) & readContentData_i;
|
elsif (tt = "01") then
|
elsif (tt = "01") then
|
masterDat_o <= packetContent(63 downto 32);
|
inboundDat_o <= packetContent(63 downto 32);
|
packetContent <= packetContent(31 downto 16) & readContentData_i & x"0000";
|
packetContent <= packetContent(31 downto 16) & readContentData_i & x"0000";
|
end if;
|
end if;
|
|
|
if (readContentEnd_i = '0') then
|
if (readContentEnd_i = '0') then
|
if (packetPosition = 20) then
|
if (packetPosition = 18) then
|
state <= FORWARD_CRC;
|
state <= FORWARD_CRC;
|
end if;
|
end if;
|
|
|
readContent_o <= '1';
|
readContent_o <= '1';
|
else
|
else
|
| Line 368... |
Line 398... |
|
|
when FORWARD_CRC =>
|
when FORWARD_CRC =>
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
--
|
--
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
if (masterAck_i = '1') then
|
if (inboundAck_i = '1') then
|
masterDat_o <= packetContent(63 downto 32);
|
inboundDat_o <= packetContent(63 downto 32);
|
|
|
packetPosition <= packetPosition + 1;
|
packetPosition <= packetPosition + 1;
|
packetContent <=
|
packetContent <=
|
packetContent(31 downto 0) & readContentData_i(15 downto 0) & x"0000";
|
packetContent(31 downto 16) & readContentData_i(15 downto 0) & x"00000000";
|
|
|
if (readContentEnd_i = '0') then
|
if (readContentEnd_i = '0') then
|
readContent_o <= '1';
|
readContent_o <= '1';
|
state <= FORWARD_LONG;
|
state <= FORWARD_LONG;
|
else
|
else
|
| Line 388... |
Line 418... |
|
|
when FORWARD_LONG =>
|
when FORWARD_LONG =>
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
--
|
--
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
if (masterAck_i = '1') then
|
if (inboundAck_i = '1') then
|
masterDat_o <= packetContent(63 downto 32);
|
inboundDat_o <= packetContent(63 downto 32);
|
|
|
packetPosition <= packetPosition + 1;
|
packetPosition <= packetPosition + 1;
|
packetContent <=
|
packetContent <=
|
packetContent(15 downto 0) & readContentData_i & x"0000";
|
readContentData_i & x"00000000";
|
|
|
if (readContentEnd_i = '0') then
|
if (readContentEnd_i = '0') then
|
readContent_o <= '1';
|
readContent_o <= '1';
|
else
|
else
|
readFrame_o <= '1';
|
readFrame_o <= '1';
|
| Line 407... |
Line 437... |
|
|
when FORWARD_LAST =>
|
when FORWARD_LAST =>
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
--
|
--
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
-- REMARK: The last always contain the CRC?
|
if (inboundAck_i = '1') then
|
if (masterAck_i = '1') then
|
inboundDat_o <= packetContent(63 downto 32);
|
masterDat_o <= packetContent(63 downto 32);
|
|
state <= END_PACKET;
|
state <= END_PACKET;
|
end if;
|
end if;
|
|
|
when END_PACKET =>
|
when END_PACKET =>
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
--
|
--
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
if (masterAck_i = '1') then
|
if (inboundAck_i = '1') then
|
masterCyc_o <= '0';
|
inboundCyc_o <= '0';
|
masterStb_o <= '0';
|
inboundStb_o <= '0';
|
state <= IDLE;
|
state <= IDLE;
|
end if;
|
end if;
|
|
|
when others =>
|
when others =>
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
| Line 462... |
Line 491... |
writeFrame_o : out std_logic;
|
writeFrame_o : out std_logic;
|
writeFrameAbort_o : out std_logic;
|
writeFrameAbort_o : out std_logic;
|
writeContent_o : out std_logic;
|
writeContent_o : out std_logic;
|
writeContentData_o : out std_logic_vector(31 downto 0);
|
writeContentData_o : out std_logic_vector(31 downto 0);
|
|
|
slaveCyc_i : in std_logic;
|
outboundCyc_i : in std_logic;
|
slaveStb_i : in std_logic;
|
outboundStb_i : in std_logic;
|
slaveDat_i : in std_logic_vector(31 downto 0);
|
outboundDat_i : in std_logic_vector(31 downto 0);
|
slaveAck_o : out std_logic);
|
outboundAck_o : out std_logic);
|
end entity;
|
end entity;
|
|
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Architecture for RioLogicalCommonEgress.
|
-- Architecture for RioLogicalCommonEgress.
|
| Line 538... |
Line 567... |
writeContentData1 <= (others=>'0');
|
writeContentData1 <= (others=>'0');
|
writeContentData2 <= (others=>'0');
|
writeContentData2 <= (others=>'0');
|
|
|
crcReset <= '0';
|
crcReset <= '0';
|
|
|
slaveAck_o <= '0';
|
outboundAck_o <= '0';
|
|
|
writeFrame_o <= '0';
|
writeFrame_o <= '0';
|
writeFrameAbort_o <= '0';
|
writeFrameAbort_o <= '0';
|
elsif (clk'event and clk = '1') then
|
elsif (clk'event and clk = '1') then
|
writeContent <= '0';
|
writeContent <= '0';
|
| Line 563... |
Line 592... |
|
|
when HEADER_GET =>
|
when HEADER_GET =>
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
--
|
--
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
if ((slaveCyc_i = '1') and (slaveStb_i = '1')) then
|
if ((outboundCyc_i = '1') and (outboundStb_i = '1')) then
|
temp <= slaveDat_i(15 downto 0);
|
temp <= outboundDat_i(15 downto 0);
|
tt <= slaveDat_i(5 downto 4);
|
tt <= outboundDat_i(5 downto 4);
|
|
|
slaveAck_o <= '1';
|
outboundAck_o <= '1';
|
state <= HEADER_ACK;
|
state <= HEADER_ACK;
|
else
|
else
|
state <= HEADER_GET;
|
state <= HEADER_GET;
|
end if;
|
end if;
|
|
|
when HEADER_ACK =>
|
when HEADER_ACK =>
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
--
|
--
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
slaveAck_o <= '0';
|
outboundAck_o <= '0';
|
state <= DESTINATION_GET;
|
state <= DESTINATION_GET;
|
|
|
when DESTINATION_GET =>
|
when DESTINATION_GET =>
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
--
|
--
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
|
|
if ((slaveCyc_i = '1') and (slaveStb_i = '1')) then
|
if ((outboundCyc_i = '1') and (outboundStb_i = '1')) then
|
if (tt = "01") then
|
if (tt = "01") then
|
writeContentData2 <= temp & slaveDat_i(15 downto 0);
|
writeContentData2 <= temp & outboundDat_i(15 downto 0);
|
else
|
else
|
report "TT-field not supported." severity error;
|
report "TT-field not supported." severity error;
|
end if;
|
end if;
|
|
|
slaveAck_o <= '1';
|
outboundAck_o <= '1';
|
state <= DESTINATION_ACK;
|
state <= DESTINATION_ACK;
|
else
|
else
|
state <= RESTART_FRAME;
|
state <= RESTART_FRAME;
|
end if;
|
end if;
|
|
|
when DESTINATION_ACK =>
|
when DESTINATION_ACK =>
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
--
|
--
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
slaveAck_o <= '0';
|
outboundAck_o <= '0';
|
state <= SOURCE_GET;
|
state <= SOURCE_GET;
|
|
|
when SOURCE_GET =>
|
when SOURCE_GET =>
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
--
|
--
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
|
|
if ((slaveCyc_i = '1') and (slaveStb_i = '1')) then
|
if ((outboundCyc_i = '1') and (outboundStb_i = '1')) then
|
if (tt = "01") then
|
if (tt = "01") then
|
temp <= slaveDat_i(15 downto 0);
|
temp <= outboundDat_i(15 downto 0);
|
end if;
|
end if;
|
|
|
slaveAck_o <= '1';
|
outboundAck_o <= '1';
|
state <= SOURCE_ACK;
|
state <= SOURCE_ACK;
|
else
|
else
|
state <= RESTART_FRAME;
|
state <= RESTART_FRAME;
|
end if;
|
end if;
|
|
|
when SOURCE_ACK =>
|
when SOURCE_ACK =>
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
--
|
--
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
slaveAck_o <= '0';
|
outboundAck_o <= '0';
|
state <= CONTENT_GET;
|
state <= CONTENT_GET;
|
|
|
when CONTENT_GET =>
|
when CONTENT_GET =>
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
--
|
--
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
if ((slaveCyc_i = '1') and (slaveStb_i = '1')) then
|
if ((outboundCyc_i = '1') and (outboundStb_i = '1')) then
|
if (packetPosition < 19) then
|
if (packetPosition < 19) then
|
if (tt = "01") then
|
if (tt = "01") then
|
writeContentData2 <= temp & slaveDat_i(31 downto 16);
|
writeContentData2 <= temp & outboundDat_i(31 downto 16);
|
temp <= slaveDat_i(15 downto 0);
|
temp <= outboundDat_i(15 downto 0);
|
slaveAck_o <= '1';
|
outboundAck_o <= '1';
|
end if;
|
end if;
|
elsif (packetPosition = 19) then
|
elsif (packetPosition = 19) then
|
if (tt = "01") then
|
if (tt = "01") then
|
writeContentData2 <= crc16Next & temp;
|
writeContentData2 <= crc16Next & temp;
|
end if;
|
end if;
|
else
|
else
|
if (tt = "01") then
|
if (tt = "01") then
|
writeContentData2 <= slaveDat_i;
|
writeContentData2 <= outboundDat_i;
|
slaveAck_o <= '1';
|
outboundAck_o <= '1';
|
end if;
|
end if;
|
end if;
|
end if;
|
writeContent <= '1';
|
writeContent <= '1';
|
writeContentData1 <= writeContentData2;
|
writeContentData1 <= writeContentData2;
|
packetPosition <= packetPosition + 1;
|
packetPosition <= packetPosition + 1;
|
| Line 666... |
Line 695... |
if (packetPosition = 20) then
|
if (packetPosition = 20) then
|
if (tt = "01") then
|
if (tt = "01") then
|
writeContentData2 <= crc16Next & temp;
|
writeContentData2 <= crc16Next & temp;
|
end if;
|
end if;
|
end if;
|
end if;
|
slaveAck_o <= '0';
|
outboundAck_o <= '0';
|
state <= CONTENT_GET;
|
state <= CONTENT_GET;
|
|
|
when CRC_APPEND =>
|
when CRC_APPEND =>
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
--
|
--
|
| Line 764... |
Line 793... |
port map(
|
port map(
|
d_i=>writeContentData1(15 downto 0), crc_i=>crc16Temp, crc_o=>crc16Next);
|
d_i=>writeContentData1(15 downto 0), crc_i=>crc16Temp, crc_o=>crc16Next);
|
|
|
end architecture;
|
end architecture;
|
|
|
No newline at end of file
|
No newline at end of file
|
|
|
|
|
|
-------------------------------------------------------------------------------
|
|
--
|
|
-------------------------------------------------------------------------------
|
|
|
|
library ieee;
|
|
use ieee.std_logic_1164.all;
|
|
use ieee.numeric_std.all;
|
|
use work.rio_common.all;
|
|
|
|
|
|
-------------------------------------------------------------------------------
|
|
--
|
|
-------------------------------------------------------------------------------
|
|
entity RioLogicalCommonInterconnect is
|
|
generic(
|
|
WIDTH : natural);
|
|
port(
|
|
clk : in std_logic;
|
|
areset_n : in std_logic;
|
|
|
|
stb_i : in std_logic_vector(WIDTH-1 downto 0);
|
|
dataM_i : in std_logic_vector(32*WIDTH-1 downto 0);
|
|
ack_o : out std_logic_vector(WIDTH-1 downto 0);
|
|
|
|
stb_o : out std_logic;
|
|
dataS_o : out std_logic_vector(31 downto 0);
|
|
ack_i : in std_logic);
|
|
end entity;
|
|
|
|
|
|
-------------------------------------------------------------------------------
|
|
--
|
|
-------------------------------------------------------------------------------
|
|
architecture RioLogicalCommonInterconnectImpl of RioLogicalCommonInterconnect is
|
|
signal activeCycle : std_logic;
|
|
signal selectedMaster : natural range 0 to WIDTH-1;
|
|
begin
|
|
|
|
-----------------------------------------------------------------------------
|
|
-- Arbitration.
|
|
-----------------------------------------------------------------------------
|
|
Arbiter: process(areset_n, clk)
|
|
begin
|
|
if (areset_n = '0') then
|
|
activeCycle <= '0';
|
|
selectedMaster <= 0;
|
|
elsif (clk'event and clk = '1') then
|
|
if (activeCycle = '0') then
|
|
for i in 0 to WIDTH-1 loop
|
|
if (stb_i(i) = '1') then
|
|
activeCycle <= '1';
|
|
selectedMaster <= i;
|
|
end if;
|
|
end loop;
|
|
else
|
|
if (stb_i(selectedMaster) = '0') then
|
|
activeCycle <= '0';
|
|
end if;
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
-----------------------------------------------------------------------------
|
|
-- Interconnection.
|
|
-----------------------------------------------------------------------------
|
|
stb_o <= stb_i(selectedMaster) and activeCycle;
|
|
dataS_o <= dataM_i(32*(selectedMaster+1)-1 downto 32*selectedMaster);
|
|
|
|
Interconnect: for i in 0 to WIDTH-1 generate
|
|
ack_o(i) <= ack_i when (selectedMaster = i) else '0';
|
|
end generate;
|
|
|
|
end architecture;
|
|
|
|
|
|
|
No newline at end of file
|
No newline at end of file
|
