| Line 8... |
Line 8... |
-- Description
|
-- Description
|
-- Containing RapidIO packet switching functionality contained in the top
|
-- Containing RapidIO packet switching functionality contained in the top
|
-- entity RioSwitch.
|
-- entity RioSwitch.
|
--
|
--
|
-- To Do:
|
-- To Do:
|
-- - Add configAck to external interface.
|
|
-- - Complete forwarding of maintenance packets.
|
|
-- - Remove all common component-declarations and move them to RioCommon.
|
|
-- - Add support for longer maintenance packets.
|
|
-- - Add support for portWrite maintenance packets.
|
-- - Add support for portWrite maintenance packets.
|
-- - Add a real crossbar as interconnect.
|
-- - Add a real crossbar as interconnect.
|
-- - Change the internal addressing to one-hot.
|
-- - Change the internal addressing to one-hot.
|
-- - Remove acknowledge cycle when transfering packets between ports to double
|
-- - Remove acknowledge cycle when transfering packets between ports to double
|
-- the bandwidth.
|
-- the bandwidth.
|
| Line 54... |
Line 50... |
-- You should have received a copy of the GNU Lesser General
|
-- You should have received a copy of the GNU Lesser General
|
-- Public License along with this source; if not, download it
|
-- Public License along with this source; if not, download it
|
-- from http://www.opencores.org/lgpl.shtml
|
-- from http://www.opencores.org/lgpl.shtml
|
--
|
--
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
-- Revision history.
|
|
-- - Adding support for all sizes of maintenance packets.
|
|
-- - Adding configAck to external config-space interface.
|
|
-------------------------------------------------------------------------------
|
|
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- RioSwitch
|
-- RioSwitch
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
| Line 115... |
Line 115... |
|
|
configStb_o : out std_logic;
|
configStb_o : out std_logic;
|
configWe_o : out std_logic;
|
configWe_o : out std_logic;
|
configAddr_o : out std_logic_vector(23 downto 0);
|
configAddr_o : out std_logic_vector(23 downto 0);
|
configData_o : out std_logic_vector(31 downto 0);
|
configData_o : out std_logic_vector(31 downto 0);
|
configData_i : in std_logic_vector(31 downto 0));
|
configData_i : in std_logic_vector(31 downto 0);
|
|
configAck_i : in std_logic);
|
end entity;
|
end entity;
|
|
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Architecture for RioSwitch.
|
-- Architecture for RioSwitch.
|
| Line 223... |
Line 224... |
|
|
configStb_o : out std_logic;
|
configStb_o : out std_logic;
|
configWe_o : out std_logic;
|
configWe_o : out std_logic;
|
configAddr_o : out std_logic_vector(23 downto 0);
|
configAddr_o : out std_logic_vector(23 downto 0);
|
configData_o : out std_logic_vector(31 downto 0);
|
configData_o : out std_logic_vector(31 downto 0);
|
configData_i : in std_logic_vector(31 downto 0));
|
configData_i : in std_logic_vector(31 downto 0);
|
|
configAck_i : in std_logic);
|
end component;
|
end component;
|
|
|
component SwitchPort is
|
component SwitchPort is
|
generic(
|
generic(
|
MAINTENANCE_LOOKUP : boolean;
|
MAINTENANCE_LOOKUP : boolean;
|
| Line 392... |
Line 394... |
localAckIdWrite_o=>localAckIdWrite_o, clrOutstandingAckId_o=>clrOutstandingAckId_o,
|
localAckIdWrite_o=>localAckIdWrite_o, clrOutstandingAckId_o=>clrOutstandingAckId_o,
|
inboundAckId_o=>inboundAckId_o, outstandingAckId_o=>outstandingAckId_o,
|
inboundAckId_o=>inboundAckId_o, outstandingAckId_o=>outstandingAckId_o,
|
outboundAckId_o=>outboundAckId_o, inboundAckId_i=>inboundAckId_i,
|
outboundAckId_o=>outboundAckId_o, inboundAckId_i=>inboundAckId_i,
|
outstandingAckId_i=>outstandingAckId_i, outboundAckId_i=>outboundAckId_i,
|
outstandingAckId_i=>outstandingAckId_i, outboundAckId_i=>outboundAckId_i,
|
configStb_o=>configStb_o, configWe_o=>configWe_o, configAddr_o=>configAddr_o,
|
configStb_o=>configStb_o, configWe_o=>configWe_o, configAddr_o=>configAddr_o,
|
configData_o=>configData_o, configData_i=>configData_i);
|
configData_o=>configData_o, configData_i=>configData_i, configAck_i=>configAck_i);
|
|
|
end architecture;
|
end architecture;
|
|
|
|
|
|
|
| Line 903... |
Line 905... |
-- Configuration space for implementation-defined space.
|
-- Configuration space for implementation-defined space.
|
configStb_o : out std_logic;
|
configStb_o : out std_logic;
|
configWe_o : out std_logic;
|
configWe_o : out std_logic;
|
configAddr_o : out std_logic_vector(23 downto 0);
|
configAddr_o : out std_logic_vector(23 downto 0);
|
configData_o : out std_logic_vector(31 downto 0);
|
configData_o : out std_logic_vector(31 downto 0);
|
configData_i : in std_logic_vector(31 downto 0));
|
configData_i : in std_logic_vector(31 downto 0);
|
|
configAck_i : in std_logic);
|
end entity;
|
end entity;
|
|
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Architecture for SwitchPort.
|
-- Architecture for SwitchPort.
|
| Line 961... |
Line 964... |
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- Signals between the port and the packet-queue.
|
-- Signals between the port and the packet-queue.
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
|
|
signal outboundFramePort : std_logic_vector(7 downto 0);
|
signal outboundFramePort, outboundFramePort0 : std_logic_vector(7 downto 0);
|
signal outboundReadFrameEmpty : std_logic;
|
signal outboundReadFrameEmpty : std_logic;
|
signal outboundReadFrame : std_logic;
|
signal outboundReadFrame : std_logic;
|
signal outboundReadContent : std_logic;
|
signal outboundReadContent : std_logic;
|
signal outboundReadContentEnd : std_logic;
|
signal outboundReadContentEnd : std_logic;
|
signal outboundReadContentData : std_logic_vector(31 downto 0);
|
signal outboundReadContentData : std_logic_vector(31 downto 0);
|
signal inboundFramePort : std_logic_vector(7 downto 0);
|
signal inboundFramePort, inboundFramePort0 : std_logic_vector(7 downto 0);
|
signal inboundWriteFrameFull : std_logic;
|
signal inboundWriteFrameFull : std_logic;
|
signal inboundWriteFrame : std_logic;
|
signal inboundWriteFrame : std_logic;
|
signal inboundWriteFrameAbort : std_logic;
|
signal inboundWriteFrameAbort : std_logic;
|
signal inboundWriteContent : std_logic;
|
signal inboundWriteContent : std_logic;
|
signal inboundWriteContentData : std_logic_vector(31 downto 0);
|
signal inboundWriteContentData : std_logic_vector(31 downto 0);
|
| Line 1012... |
Line 1015... |
signal vc : std_logic;
|
signal vc : std_logic;
|
signal crf : std_logic;
|
signal crf : std_logic;
|
signal prio : std_logic_vector(1 downto 0);
|
signal prio : std_logic_vector(1 downto 0);
|
signal tt : std_logic_vector(1 downto 0);
|
signal tt : std_logic_vector(1 downto 0);
|
signal tid : std_logic_vector(7 downto 0);
|
signal tid : std_logic_vector(7 downto 0);
|
|
signal status : std_logic_vector(3 downto 0);
|
|
|
signal readRequestInbound : std_logic;
|
signal readRequestInbound : std_logic;
|
signal writeRequestInbound : std_logic;
|
signal writeRequestInbound : std_logic;
|
signal readResponseInbound : std_logic;
|
signal readResponseInbound : std_logic;
|
signal writeResponseInbound : std_logic;
|
signal writeResponseInbound : std_logic;
|
signal portWriteInbound : std_logic;
|
signal portWriteInbound : std_logic;
|
signal dstIdInbound : std_logic_vector(31 downto 0);
|
signal dstIdInbound : std_logic_vector(31 downto 0);
|
signal srcIdInbound : std_logic_vector(31 downto 0);
|
signal srcIdInbound : std_logic_vector(31 downto 0);
|
|
signal sizeInbound : std_logic_vector(3 downto 0);
|
|
signal statusInbound : std_logic_vector(3 downto 0);
|
signal hopInbound : std_logic_vector(7 downto 0);
|
signal hopInbound : std_logic_vector(7 downto 0);
|
signal offsetInbound : std_logic_vector(20 downto 0);
|
signal offsetInbound : std_logic_vector(20 downto 0);
|
signal wdptrInbound: std_logic;
|
signal wdptrInbound: std_logic;
|
signal payloadLengthInbound : std_logic_vector(3 downto 0);
|
signal payloadLengthInbound : std_logic_vector(2 downto 0);
|
signal payloadIndexInbound : std_logic_vector(3 downto 0);
|
signal payloadIndexInbound : std_logic_vector(2 downto 0);
|
signal payloadInbound : std_logic_vector(31 downto 0);
|
signal payloadInbound : std_logic_vector(63 downto 0);
|
signal doneInbound : std_logic;
|
signal doneInbound : std_logic;
|
|
|
signal readRequestOutbound : std_logic;
|
signal readRequestOutbound : std_logic;
|
signal writeRequestOutbound : std_logic;
|
signal writeRequestOutbound : std_logic;
|
signal readResponseOutbound : std_logic;
|
signal readResponseOutbound : std_logic;
|
signal writeResponseOutbound : std_logic;
|
signal writeResponseOutbound : std_logic;
|
signal portWriteOutbound : std_logic;
|
signal portWriteOutbound : std_logic;
|
signal dstIdOutbound : std_logic_vector(31 downto 0);
|
signal dstIdOutbound : std_logic_vector(31 downto 0);
|
signal srcIdOutbound : std_logic_vector(31 downto 0);
|
signal srcIdOutbound : std_logic_vector(31 downto 0);
|
|
signal statusOutbound : std_logic_vector(3 downto 0);
|
signal hopOutbound : std_logic_vector(7 downto 0);
|
signal hopOutbound : std_logic_vector(7 downto 0);
|
signal wdptrOutbound: std_logic;
|
signal payloadLengthOutbound : std_logic_vector(2 downto 0);
|
signal payloadLengthOutbound : std_logic_vector(3 downto 0);
|
signal payloadIndexOutbound : std_logic_vector(2 downto 0);
|
signal payloadIndexOutbound : std_logic_vector(3 downto 0);
|
signal payloadOutbound : std_logic_vector(63 downto 0);
|
signal payloadOutbound : std_logic_vector(31 downto 0);
|
|
signal doneOutbound : std_logic;
|
signal doneOutbound : std_logic;
|
|
|
signal readRequestMaint : std_logic;
|
signal readRequestMaint : std_logic;
|
signal writeRequestMaint : std_logic;
|
signal writeRequestMaint : std_logic;
|
signal readResponseMaint : std_logic;
|
signal readResponseMaint : std_logic;
|
signal writeResponseMaint : std_logic;
|
signal writeResponseMaint : std_logic;
|
signal wdptrMaint : std_logic;
|
signal statusMaint : std_logic_vector(3 downto 0);
|
signal payloadLengthMaint : std_logic_vector(3 downto 0);
|
signal payloadLengthMaint : std_logic_vector(2 downto 0);
|
signal payloadIndexMaint : std_logic_vector(3 downto 0);
|
signal payloadIndexMaint : std_logic_vector(2 downto 0);
|
signal payloadMaint : std_logic_vector(31 downto 0);
|
signal payloadMaint : std_logic_vector(63 downto 0);
|
signal doneMaint : std_logic;
|
signal doneMaint : std_logic;
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
--
|
--
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
| Line 1080... |
Line 1086... |
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- Configuration space signals.
|
-- Configuration space signals.
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
|
|
signal configStb : std_logic;
|
signal configStb, configStbInternal : std_logic;
|
signal configWe : std_logic;
|
signal configWe : std_logic;
|
signal configAdr : std_logic_vector(23 downto 0);
|
signal configAdr : std_logic_vector(23 downto 0);
|
signal configDataWrite : std_logic_vector(31 downto 0);
|
signal configDataWrite : std_logic_vector(31 downto 0);
|
signal configDataRead, configDataReadInternal : std_logic_vector(31 downto 0);
|
signal configDataRead, configDataReadInternal : std_logic_vector(31 downto 0);
|
signal configAck : std_logic;
|
signal configAck, configAckInternal : std_logic;
|
|
|
-- REMARK: Make these variables instead...
|
-- REMARK: Make these variables instead...
|
signal discovered : std_logic;
|
signal discovered : std_logic;
|
signal hostBaseDeviceIdLocked : std_logic;
|
signal hostBaseDeviceIdLocked : std_logic;
|
signal hostBaseDeviceId : std_logic_vector(15 downto 0);
|
signal hostBaseDeviceId : std_logic_vector(15 downto 0);
|
| Line 1125... |
Line 1131... |
slaveData_i=>slaveData_i,
|
slaveData_i=>slaveData_i,
|
slaveData_o=>slaveData_o,
|
slaveData_o=>slaveData_o,
|
slaveAck_o=>slaveAck_o,
|
slaveAck_o=>slaveAck_o,
|
lookupStb_o=>open,
|
lookupStb_o=>open,
|
lookupAddr_o=>open,
|
lookupAddr_o=>open,
|
lookupData_i=>outboundFramePort,
|
lookupData_i=>outboundFramePort0,
|
lookupAck_i=>'1',
|
lookupAck_i=>'1',
|
readFrameEmpty_i=>outboundReadFrameEmpty,
|
readFrameEmpty_i=>outboundReadFrameEmpty,
|
readFrame_o=>outboundReadFrame,
|
readFrame_o=>outboundReadFrame,
|
readFrameRestart_o=>open,
|
readFrameRestart_o=>open,
|
readFrameAborted_i=>'0',
|
readFrameAborted_i=>'0',
|
readContentEmpty_i=>'0',
|
readContentEmpty_i=>'0',
|
readContent_o=>outboundReadContent,
|
readContent_o=>outboundReadContent,
|
readContentEnd_i=>outboundReadContentEnd,
|
readContentEnd_i=>outboundReadContentEnd,
|
readContentData_i=>outboundReadContentData,
|
readContentData_i=>outboundReadContentData,
|
writeFramePort_o=>inboundFramePort,
|
writeFramePort_o=>inboundFramePort0,
|
writeFrameFull_i=>inboundWriteFrameFull,
|
writeFrameFull_i=>inboundWriteFrameFull,
|
writeFrame_o=>inboundWriteFrame,
|
writeFrame_o=>inboundWriteFrame,
|
writeFrameAbort_o=>inboundWriteFrameAbort,
|
writeFrameAbort_o=>inboundWriteFrameAbort,
|
writeContent_o=>inboundWriteContent,
|
writeContent_o=>inboundWriteContent,
|
writeContentData_o=>inboundWriteContentData);
|
writeContentData_o=>inboundWriteContentData);
|
|
|
|
process(clk)
|
|
begin
|
|
if (clk'event and clk = '1') then
|
|
if (inboundReadFrame = '1') then
|
|
inboundFramePort <= inboundFramePort0;
|
|
end if;
|
|
if (outboundWriteFrame = '1') then
|
|
outboundFramePort0 <= outboundFramePort;
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- Packet queue.
|
-- Packet queue.
|
-- This queue should only contain one packet.
|
-- This queue should only contain one packet.
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- REMARK: Use a packet-buffer with a configurable maximum sized packet...
|
-- REMARK: Use a packet-buffer with a configurable maximum sized packet...
|
|
-- the size of the memory is too large...
|
PacketQueue: RioPacketBuffer
|
PacketQueue: RioPacketBuffer
|
generic map(SIZE_ADDRESS_WIDTH=>1, CONTENT_ADDRESS_WIDTH=>7)
|
generic map(SIZE_ADDRESS_WIDTH=>1, CONTENT_ADDRESS_WIDTH=>7)
|
port map(
|
port map(
|
clk=>clk, areset_n=>areset_n,
|
clk=>clk, areset_n=>areset_n,
|
inboundWriteFrameFull_o=>inboundWriteFrameFull,
|
inboundWriteFrameFull_o=>inboundWriteFrameFull,
|
| Line 1229... |
Line 1248... |
crf_o=>crf,
|
crf_o=>crf,
|
prio_o=>prio,
|
prio_o=>prio,
|
tt_o=>tt,
|
tt_o=>tt,
|
dstid_o=>dstIdInbound,
|
dstid_o=>dstIdInbound,
|
srcid_o=>srcIdInbound,
|
srcid_o=>srcIdInbound,
|
|
size_o=>sizeInbound,
|
|
status_o=>statusInbound,
|
tid_o=>tid,
|
tid_o=>tid,
|
hop_o=>hopInbound,
|
hop_o=>hopInbound,
|
offset_o=>offsetInbound,
|
offset_o=>offsetInbound,
|
wdptr_o=>wdptrInbound,
|
wdptr_o=>wdptrInbound,
|
payloadLength_o=>payloadLengthInbound,
|
payloadLength_o=>payloadLengthInbound,
|
| Line 1253... |
Line 1274... |
readResponseOutbound <= (readResponseInbound and sendPacket) when (forwardPacket = '1') else readResponseMaint;
|
readResponseOutbound <= (readResponseInbound and sendPacket) when (forwardPacket = '1') else readResponseMaint;
|
writeResponseOutbound <= (writeResponseInbound and sendPacket) when (forwardPacket = '1') else writeResponseMaint;
|
writeResponseOutbound <= (writeResponseInbound and sendPacket) when (forwardPacket = '1') else writeResponseMaint;
|
portWriteOutbound <= (portWriteInbound and sendPacket) when (forwardPacket = '1') else '0';
|
portWriteOutbound <= (portWriteInbound and sendPacket) when (forwardPacket = '1') else '0';
|
srcIdOutbound <= srcIdInbound when (forwardPacket = '1') else dstIdInbound;
|
srcIdOutbound <= srcIdInbound when (forwardPacket = '1') else dstIdInbound;
|
dstIdOutbound <= dstIdInbound when (forwardPacket = '1') else srcIdInbound;
|
dstIdOutbound <= dstIdInbound when (forwardPacket = '1') else srcIdInbound;
|
|
statusOutbound <= statusInbound when (forwardPacket = '1') else statusMaint;
|
hopOutbound <= std_logic_vector(unsigned(hopInbound)-1) when (forwardPacket = '1') else x"ff";
|
hopOutbound <= std_logic_vector(unsigned(hopInbound)-1) when (forwardPacket = '1') else x"ff";
|
wdptrOutbound <= wdptrInbound when (forwardPacket = '1') else wdptrMaint;
|
|
payloadLengthOutbound <= payloadLengthInbound when (forwardPacket = '1') else payloadLengthMaint;
|
payloadLengthOutbound <= payloadLengthInbound when (forwardPacket = '1') else payloadLengthMaint;
|
payloadOutbound <= payloadInbound when (forwardPacket = '1') else payloadMaint;
|
payloadOutbound <= payloadInbound when (forwardPacket = '1') else payloadMaint;
|
-- REMARK: Connect enable to something...
|
-- REMARK: Connect enable to something...
|
OutboundPacket: MaintenanceOutbound
|
OutboundPacket: MaintenanceOutbound
|
port map(
|
port map(
|
| Line 1272... |
Line 1293... |
crf_i=>crf,
|
crf_i=>crf,
|
prio_i=>prio,
|
prio_i=>prio,
|
tt_i=>tt,
|
tt_i=>tt,
|
dstid_i=>dstIdOutbound,
|
dstid_i=>dstIdOutbound,
|
srcid_i=>srcIdOutbound,
|
srcid_i=>srcIdOutbound,
|
status_i=>"0000",
|
size_i=>sizeInbound,
|
|
status_i=>statusOutbound,
|
tid_i=>tid,
|
tid_i=>tid,
|
hop_i=>hopOutbound,
|
hop_i=>hopOutbound,
|
offset_i=>offsetInbound,
|
offset_i=>offsetInbound,
|
wdptr_i=>wdptrOutbound,
|
wdptr_i=>wdptrInbound,
|
payloadLength_i=>payloadLengthOutbound,
|
payloadLength_i=>payloadLengthOutbound,
|
payloadIndex_o=>payloadIndexOutbound,
|
payloadIndex_o=>payloadIndexOutbound,
|
payload_i=>payloadOutbound,
|
payload_i=>payloadOutbound,
|
done_o=>doneOutbound,
|
done_o=>doneOutbound,
|
outboundCyc_o=>outboundCyc(0),
|
outboundCyc_o=>outboundCyc(0),
|
| Line 1366... |
Line 1388... |
--
|
--
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
-- REMARK: Wait for the packet to be fully transmitted to the target
|
-- REMARK: Wait for the packet to be fully transmitted to the target
|
-- port. Then reset everything for the reception of a new packet.
|
-- port. Then reset everything for the reception of a new packet.
|
sendPacket <= '1';
|
sendPacket <= '1';
|
if (doneOutbound = '1') then
|
if (doneInbound = '1') then
|
masterState := STATE_IDLE;
|
masterState := STATE_IDLE;
|
end if;
|
end if;
|
|
|
when others =>
|
when others =>
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
| Line 1390... |
Line 1412... |
MaintenanceBridge: RioLogicalMaintenance
|
MaintenanceBridge: RioLogicalMaintenance
|
port map(
|
port map(
|
clk=>clk, areset_n=>areset_n, enable=>'1',
|
clk=>clk, areset_n=>areset_n, enable=>'1',
|
readRequestReady_i=>readRequestMaint,
|
readRequestReady_i=>readRequestMaint,
|
writeRequestReady_i=>writeRequestMaint,
|
writeRequestReady_i=>writeRequestMaint,
|
|
size_i=>sizeInbound,
|
offset_i=>offsetInbound,
|
offset_i=>offsetInbound,
|
wdptr_i=>wdptrInbound,
|
wdptr_i=>wdptrInbound,
|
payloadLength_i=>payloadLengthInbound,
|
payloadLength_i=>payloadLengthInbound,
|
payloadIndex_o=>payloadIndexMaint,
|
payloadIndex_o=>payloadIndexMaint,
|
payload_i=>payloadInbound,
|
payload_i=>payloadInbound,
|
done_o=>doneMaint,
|
done_o=>doneMaint,
|
readResponseReady_o=>readResponseMaint,
|
readResponseReady_o=>readResponseMaint,
|
writeResponseReady_o=>writeResponseMaint,
|
writeResponseReady_o=>writeResponseMaint,
|
wdptr_o=>wdptrMaint,
|
status_o=>statusMaint,
|
payloadLength_o=>payloadLengthMaint,
|
payloadLength_o=>payloadLengthMaint,
|
payloadIndex_i=>payloadIndexOutbound,
|
payloadIndex_i=>payloadIndexOutbound,
|
payload_o=>payloadMaint,
|
payload_o=>payloadMaint,
|
done_i=>doneOutbound,
|
done_i=>doneOutbound,
|
configStb_o=>configStb,
|
configStb_o=>configStb,
|
| Line 1418... |
Line 1441... |
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
portLinkTimeout_o <= portLinkTimeout;
|
portLinkTimeout_o <= portLinkTimeout;
|
outputPortEnable_o <= outputPortEnable;
|
outputPortEnable_o <= outputPortEnable;
|
inputPortEnable_o <= inputPortEnable;
|
inputPortEnable_o <= inputPortEnable;
|
|
|
-- REMARK: Connect configAck...
|
|
configStb_o <= '1' when ((configStb = '1') and (configAdr(23 downto 16) /= x"00")) else '0';
|
configStb_o <= '1' when ((configStb = '1') and (configAdr(23 downto 16) /= x"00")) else '0';
|
|
configStbInternal <= '1' when ((configStb = '1') and (configAdr(23 downto 16) = x"00")) else '0';
|
configWe_o <= configWe;
|
configWe_o <= configWe;
|
configAddr_o <= configAdr;
|
configAddr_o <= configAdr;
|
configData_o <= configDataWrite;
|
configData_o <= configDataWrite;
|
configDataRead <= configData_i when (configAdr(23 downto 16) /= x"00") else
|
configDataRead <= configData_i when (configStbInternal = '0') else configDataReadInternal;
|
configDataReadInternal;
|
configAck <= configAck_i when (configStbInternal = '0') else configAckInternal;
|
|
|
ConfigMemory: process(areset_n, clk)
|
ConfigMemory: process(areset_n, clk)
|
begin
|
begin
|
if (areset_n = '0') then
|
if (areset_n = '0') then
|
configDataReadInternal <= (others => '0');
|
configDataReadInternal <= (others => '0');
|
configAck <= '0';
|
configAckInternal <= '0';
|
|
|
routeTableEnable <= '1';
|
routeTableEnable <= '1';
|
routeTableWrite <= '0';
|
routeTableWrite <= '0';
|
routeTableAddress <= (others => '0');
|
routeTableAddress <= (others => '0');
|
routeTablePortWrite <= (others => '0');
|
routeTablePortWrite <= (others => '0');
|
| Line 1455... |
Line 1478... |
localAckIdWrite_o <= (others => '0');
|
localAckIdWrite_o <= (others => '0');
|
elsif (clk'event and clk = '1') then
|
elsif (clk'event and clk = '1') then
|
routeTableWrite <= '0';
|
routeTableWrite <= '0';
|
localAckIdWrite_o <= (others => '0');
|
localAckIdWrite_o <= (others => '0');
|
|
|
if (configAck = '0') then
|
if (configAckInternal = '0') then
|
if (configStb = '1') then
|
if (configStbInternal = '1') then
|
configAck <= '1';
|
configAckInternal <= '1';
|
|
|
-- Check if the access is into implementation defined space or if the
|
-- Check if the access is into implementation defined space or if the
|
-- access should be handled here.
|
-- access should be handled here.
|
if (configAdr(23 downto 16) /= x"00") then
|
if (configAdr(23 downto 16) /= x"00") then
|
-- Accessing implementation defined space.
|
-- Accessing implementation defined space.
|
| Line 1847... |
Line 1870... |
end if;
|
end if;
|
else
|
else
|
-- Config memory not enabled.
|
-- Config memory not enabled.
|
end if;
|
end if;
|
else
|
else
|
configAck <= '0';
|
configAckInternal <= '0';
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
