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Subversion Repositories rio

[/] [rio/] [branches/] [2.0.0-development/] [rtl/] [vhdl/] [RioWbBridge.vhd] - Diff between revs 41 and 42

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Rev 41 Rev 42
Line 45... Line 45...
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- RioWbBridge.
-- RioWbBridge.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- REMARK: Add support for EXTENDED_ADDRESS...
-- REMARK: Add support for EXTENDED_ADDRESS...
library ieee;
library ieee;
use ieee.numeric_std.ALL;
 
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.rio_common.all;
use work.rio_common.all;
 
 
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity for RioWbBridge.
-- Entity for RioWbBridge.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
Line 1308... Line 1307...
                  if (error_i = '0') then
                  if (error_i = '0') then
                    if (payloadPresent_i = '0') then
                    if (payloadPresent_i = '0') then
                      masterDat_o <= "0000" & "0000" & tid_i & x"0000";
                      masterDat_o <= "0000" & "0000" & tid_i & x"0000";
                      state <= WAIT_COMPLETE;
                      state <= WAIT_COMPLETE;
                    else
                    else
                      masterDat_o <= "1000" & "0000" & tid_i & memoryDataRead(63 downto 48);;
                      masterDat_o <= "1000" & "0000" & tid_i & memoryDataRead(63 downto 48);
                    end if;
                    end if;
                  else
                  else
                    masterDat_o <= "0000" & "0111" & tid_i & x"0000";
                    masterDat_o <= "0000" & "0111" & tid_i & x"0000";
                    state <= WAIT_COMPLETE;
                    state <= WAIT_COMPLETE;
                  end if;
                  end if;

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