| Line 64... |
Line 64... |
ASSY_VENDOR_IDENTITY : std_logic_vector(15 downto 0);
|
ASSY_VENDOR_IDENTITY : std_logic_vector(15 downto 0);
|
ASSY_REV : std_logic_vector(15 downto 0));
|
ASSY_REV : std_logic_vector(15 downto 0));
|
port(
|
port(
|
clk : in std_logic;
|
clk : in std_logic;
|
areset_n : in std_logic;
|
areset_n : in std_logic;
|
|
enable : in std_logic;
|
|
|
readFrameEmpty_i : in std_logic;
|
readFrameEmpty_i : in std_logic;
|
readFrame_o : out std_logic;
|
readFrame_o : out std_logic;
|
readContent_o : out std_logic;
|
readContent_o : out std_logic;
|
readContentEnd_i : in std_logic;
|
readContentEnd_i : in std_logic;
|
| Line 110... |
Line 111... |
tt_o : out std_logic_vector(1 downto 0);
|
tt_o : out std_logic_vector(1 downto 0);
|
dstId_o : out std_logic_vector(31 downto 0);
|
dstId_o : out std_logic_vector(31 downto 0);
|
srcId_o : out std_logic_vector(31 downto 0);
|
srcId_o : out std_logic_vector(31 downto 0);
|
tid_o : out std_logic_vector(7 downto 0);
|
tid_o : out std_logic_vector(7 downto 0);
|
address_o : out std_logic_vector(16*EXTENDED_ADDRESS+30 downto 0);
|
address_o : out std_logic_vector(16*EXTENDED_ADDRESS+30 downto 0);
|
length_o : out std_logic_vector(3 downto 0);
|
length_o : out std_logic_vector(4 downto 0);
|
select_o : out std_logic_vector(7 downto 0);
|
select_o : out std_logic_vector(7 downto 0);
|
done_i : in std_logic;
|
done_i : in std_logic;
|
|
|
slaveCyc_i : in std_logic;
|
slaveCyc_i : in std_logic;
|
slaveStb_i : in std_logic;
|
slaveStb_i : in std_logic;
|
| Line 138... |
Line 139... |
tt_o : out std_logic_vector(1 downto 0);
|
tt_o : out std_logic_vector(1 downto 0);
|
dstId_o : out std_logic_vector(31 downto 0);
|
dstId_o : out std_logic_vector(31 downto 0);
|
srcId_o : out std_logic_vector(31 downto 0);
|
srcId_o : out std_logic_vector(31 downto 0);
|
tid_o : out std_logic_vector(7 downto 0);
|
tid_o : out std_logic_vector(7 downto 0);
|
address_o : out std_logic_vector(16*EXTENDED_ADDRESS+30 downto 0);
|
address_o : out std_logic_vector(16*EXTENDED_ADDRESS+30 downto 0);
|
length_o : out std_logic_vector(3 downto 0);
|
length_o : out std_logic_vector(4 downto 0);
|
select_o : out std_logic_vector(7 downto 0);
|
select_o : out std_logic_vector(7 downto 0);
|
payloadSetFirst_i : in std_logic;
|
payloadRead_i : in std_logic;
|
payloadSetNext_i : in std_logic;
|
payloadIndex_i : in std_logic_vector(4 downto 0);
|
payload_o : out std_logic_vector(31 downto 0);
|
payload_o : out std_logic_vector(63 downto 0);
|
done_i : in std_logic;
|
done_i : in std_logic;
|
|
|
slaveCyc_i : in std_logic;
|
slaveCyc_i : in std_logic;
|
slaveStb_i : in std_logic;
|
slaveStb_i : in std_logic;
|
slaveAdr_i : in std_logic_vector(7 downto 0);
|
slaveAdr_i : in std_logic_vector(7 downto 0);
|
| Line 168... |
Line 169... |
dstid_i : in std_logic_vector(31 downto 0);
|
dstid_i : in std_logic_vector(31 downto 0);
|
srcid_i : in std_logic_vector(31 downto 0);
|
srcid_i : in std_logic_vector(31 downto 0);
|
tid_i : in std_logic_vector(7 downto 0);
|
tid_i : in std_logic_vector(7 downto 0);
|
error_i : in std_logic;
|
error_i : in std_logic;
|
payloadPresent_i : in std_logic;
|
payloadPresent_i : in std_logic;
|
payloadLength_i : in std_logic_vector(3 downto 0);
|
payloadLength_i : in std_logic_vector(4 downto 0);
|
payloadWrite_i : in std_logic;
|
payloadWrite_i : in std_logic;
|
payloadIndex_i : in std_logic_vector(3 downto 0);
|
payloadIndex_i : in std_logic_vector(4 downto 0);
|
payload_i : in std_logic_vector(31 downto 0);
|
payload_i : in std_logic_vector(63 downto 0);
|
done_o : out std_logic;
|
done_o : out std_logic;
|
|
|
masterCyc_o : out std_logic;
|
masterCyc_o : out std_logic;
|
masterStb_o : out std_logic;
|
masterStb_o : out std_logic;
|
masterDat_o : out std_logic_vector(31 downto 0);
|
masterDat_o : out std_logic_vector(31 downto 0);
|
| Line 210... |
Line 211... |
slaveStb_i : in std_logic;
|
slaveStb_i : in std_logic;
|
slaveDat_i : in std_logic_vector(31 downto 0);
|
slaveDat_i : in std_logic_vector(31 downto 0);
|
slaveAck_o : out std_logic);
|
slaveAck_o : out std_logic);
|
end component;
|
end component;
|
|
|
|
type StateType is (IDLE,
|
|
REQUEST_CLASS, REQUEST_CLASS_RESPONSE,
|
|
WRITE_CLASS, WRITE_CLASS_RESPONSE);
|
|
signal state : StateType;
|
|
|
|
signal adr : std_logic_vector(16*EXTENDED_ADDRESS+30 downto 0);
|
|
signal datOut : std_logic_vector(63 downto 0);
|
|
|
|
signal payloadUpdate : std_logic;
|
|
signal payloadIndex : std_logic_vector(4 downto 0);
|
|
|
|
signal requestReady : std_logic;
|
|
signal requestVc : std_logic;
|
|
signal requestCrf : std_logic;
|
|
signal requestPrio : std_logic_vector(1 downto 0);
|
|
signal requestTt : std_logic_vector(1 downto 0);
|
|
signal requestDstId : std_logic_vector(31 downto 0);
|
|
signal requestSrcId : std_logic_vector(31 downto 0);
|
|
signal requestTid : std_logic_vector(7 downto 0);
|
|
signal requestAddress : std_logic_vector(16*EXTENDED_ADDRESS+30 downto 0);
|
|
signal requestLength : std_logic_vector(4 downto 0);
|
|
signal requestSelect : std_logic_vector(7 downto 0);
|
|
signal requestDone : std_logic;
|
|
signal requestAck : std_logic;
|
|
|
|
signal writeReady : std_logic;
|
|
signal writeVc : std_logic;
|
|
signal writeCrf : std_logic;
|
|
signal writePrio : std_logic_vector(1 downto 0);
|
|
signal writeTt : std_logic_vector(1 downto 0);
|
|
signal writeDstId : std_logic_vector(31 downto 0);
|
|
signal writeSrcId : std_logic_vector(31 downto 0);
|
|
signal writeTid : std_logic_vector(7 downto 0);
|
|
signal writeAddress : std_logic_vector(16*EXTENDED_ADDRESS+30 downto 0);
|
|
signal writeLength : std_logic_vector(4 downto 0);
|
|
signal writeSelect : std_logic_vector(7 downto 0);
|
|
signal writePayload : std_logic_vector(63 downto 0);
|
|
signal writeDone : std_logic;
|
|
signal writeAck : std_logic;
|
|
|
|
signal responseReady : std_logic;
|
|
signal responseVc : std_logic;
|
|
signal responseCrf : std_logic;
|
|
signal responsePrio : std_logic_vector(1 downto 0);
|
|
signal responseTt : std_logic_vector(1 downto 0);
|
|
signal responseDstId : std_logic_vector(31 downto 0);
|
|
signal responseSrcId : std_logic_vector(31 downto 0);
|
|
signal responseTid : std_logic_vector(7 downto 0);
|
|
signal responseError : std_logic;
|
|
signal responsePayloadPresent : std_logic;
|
|
signal responsePayload : std_logic_vector(63 downto 0);
|
|
signal responseDone : std_logic;
|
|
|
|
signal inboundCyc : std_logic;
|
|
signal inboundStb : std_logic;
|
|
signal inboundAdr : std_logic_vector(7 downto 0);
|
|
signal inboundDat : std_logic_vector(31 downto 0);
|
|
signal inboundAck : std_logic;
|
|
|
|
signal outboundCyc : std_logic;
|
|
signal outboundStb : std_logic;
|
|
signal outboundDat : std_logic_vector(31 downto 0);
|
|
signal outboundAck : std_logic;
|
|
|
-- signal configStb : std_logic;
|
-- signal configStb : std_logic;
|
-- signal configWe : std_logic;
|
-- signal configWe : std_logic;
|
-- signal configAdr : std_logic_vector(23 downto 0);
|
-- signal configAdr : std_logic_vector(23 downto 0);
|
-- signal configDatWrite : std_logic_vector(31 downto 0);
|
-- signal configDatWrite : std_logic_vector(31 downto 0);
|
-- signal configDatRead : std_logic_vector(31 downto 0);
|
-- signal configDatRead : std_logic_vector(31 downto 0);
|
| Line 224... |
Line 289... |
-- signal hostBaseDeviceIdLocked : std_logic;
|
-- signal hostBaseDeviceIdLocked : std_logic;
|
-- signal hostBaseDeviceId : std_logic_vector(15 downto 0) := (others => '1');
|
-- signal hostBaseDeviceId : std_logic_vector(15 downto 0) := (others => '1');
|
|
|
begin
|
begin
|
|
|
|
responseVc <= requestVc when (responsePayloadPresent = '1') else writeVc;
|
|
responseCrf <= requestCrf when (responsePayloadPresent = '1') else writeCrf;
|
|
responsePrio <= requestPrio when (responsePayloadPresent = '1') else writePrio;
|
|
responseTt <= requestTt when (responsePayloadPresent = '1') else writeTt;
|
|
responseDstId <= requestSrcId when (responsePayloadPresent = '1') else writeSrcId;
|
|
responseSrcId <= requestDstId when (responsePayloadPresent = '1') else writeDstId;
|
|
responseTid <= requestTid when (responsePayloadPresent = '1') else writeTid;
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
--
|
--
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
adr_o <= adr;
|
adr_o <= adr;
|
dat_o <= datOut;
|
dat_o <= datOut;
|
| Line 239... |
Line 312... |
stb_o <= '0';
|
stb_o <= '0';
|
we_o <= '0';
|
we_o <= '0';
|
adr <= (others=>'0');
|
adr <= (others=>'0');
|
datOut <= (others=>'0');
|
datOut <= (others=>'0');
|
|
|
responseReadReady <= '0';
|
payloadUpdate <= '0';
|
responseWriteReady <= '0';
|
payloadIndex <= (others=>'0');
|
responsePayloadWrite <= '0';
|
|
|
|
requestDone <= '0';
|
requestDone <= '0';
|
|
|
requestPayloadIndex <= (others=>'0');
|
writeDone <= '0';
|
|
|
|
responseReady <= '0';
|
|
responseError <= '0';
|
|
responsePayloadPresent <= '0';
|
|
responsePayload <= (others=>'0');
|
elsif (clk'event and clk = '1') then
|
elsif (clk'event and clk = '1') then
|
|
if (enable = '1') then
|
requestDone <= '0';
|
requestDone <= '0';
|
responsePayloadWrite <= '0';
|
writeDone <= '0';
|
|
responseReady <= '0';
|
|
|
if (responsePayloadWrite = '1') then
|
payloadUpdate <= '0';
|
responsePayloadIndex <= std_logic_vector(unsigned(responsePayloadIndex) + 1);
|
if (payloadUpdate = '1') then
|
|
payloadIndex <= std_logic_vector(unsigned(payloadIndex) + 1);
|
end if;
|
end if;
|
|
|
case state is
|
case state is
|
when IDLE =>
|
when IDLE =>
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
| Line 264... |
Line 344... |
if (requestReady = '1') then
|
if (requestReady = '1') then
|
cyc_o <= '1';
|
cyc_o <= '1';
|
stb_o <= '1';
|
stb_o <= '1';
|
we_o <= '0';
|
we_o <= '0';
|
adr <= requestAddress;
|
adr <= requestAddress;
|
|
sel_o <= requestSelect;
|
|
|
|
payloadIndex <= (others=>'0');
|
|
|
responsePayloadPresent <= '1';
|
responsePayloadPresent <= '1';
|
state <= REQUEST_CLASS;
|
state <= REQUEST_CLASS;
|
elsif (writeReady = '1') then
|
elsif (writeReady = '1') then
|
cyc_o <= '1';
|
cyc_o <= '1';
|
stb_o <= '1';
|
stb_o <= '1';
|
we_o <= '1';
|
we_o <= '1';
|
adr <= writeAddress;
|
adr <= writeAddress;
|
|
sel_o <= writeSelect;
|
datOut <= writePayload;
|
datOut <= writePayload;
|
writePayloadNext <= '1';
|
|
|
payloadUpdate <= '1';
|
|
payloadIndex <= (others=>'0');
|
|
|
responsePayloadPresent <= '0';
|
responsePayloadPresent <= '0';
|
state <= WRITE_CLASS;
|
state <= WRITE_CLASS;
|
end if;
|
end if;
|
|
|
when REQUEST_CLASS =>
|
when REQUEST_CLASS =>
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
--
|
--
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
if (ack_i = '1') then
|
if (ack_i = '1') then
|
responsePayloadWrite <= '1';
|
-- Note that responsePayloadIndex is updated after the write has been made.
|
|
payloadUpdate <= '1';
|
|
responsePayload <= dat_i;
|
|
|
if (responsePayloadIndex /= requestPayloadLength) then
|
|
adr <= std_logic_vector(unsigned(adr) + 1);
|
adr <= std_logic_vector(unsigned(adr) + 1);
|
else
|
|
|
if (payloadIndex = requestLength) then
|
requestDone <= '1';
|
requestDone <= '1';
|
cyc_o <= '0';
|
cyc_o <= '0';
|
stb_o <= '0';
|
stb_o <= '0';
|
state <= NREAD_RESPONSE;
|
state <= REQUEST_CLASS_RESPONSE;
|
end if;
|
end if;
|
-- elsif(err_i = '1') then
|
-- elsif(err_i = '1') then
|
-- REMARK: Implement error indication from wb-bus...
|
-- REMARK: Implement error indication from wb-bus...
|
end if;
|
end if;
|
|
|
when REQUEST_CLASS_RESPONSE =>
|
when REQUEST_CLASS_RESPONSE =>
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
--
|
--
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
if (responseDone = '1') then
|
if (responseDone = '1') then
|
responseReadReady <= '0';
|
responseReady <= '0';
|
state <= IDLE;
|
state <= IDLE;
|
else
|
else
|
responseReadReady <= '1';
|
responseReady <= '1';
|
end if;
|
end if;
|
|
|
when WRITE_CLASS =>
|
when WRITE_CLASS =>
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
--
|
--
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
if (ack_i = '1') then
|
if (ack_i = '1') then
|
responsePayloadWrite <= '1';
|
payloadUpdate <= '1';
|
|
|
|
adr <= std_logic_vector(unsigned(adr) + 1);
|
|
|
if (responsePayloadIndex /= requestPayloadLength) then
|
if (payloadIndex /= writeLength) then
|
adr <= std_logic_vector(unsigned(configAdr) + 1);
|
|
datOut <= writePayload;
|
datOut <= writePayload;
|
requestPayloadIndex <= std_logic_vector(unsigned(requestPayloadIndex) + 1);
|
|
else
|
else
|
writeDone <= '1';
|
writeDone <= '1';
|
cyc_o <= '0';
|
cyc_o <= '0';
|
stb_o <= '0';
|
stb_o <= '0';
|
state <= WRITE_CLASS_RESPONSE;
|
state <= WRITE_CLASS_RESPONSE;
|
| Line 330... |
Line 420... |
|
|
when WRITE_CLASS_RESPONSE =>
|
when WRITE_CLASS_RESPONSE =>
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
--
|
--
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
if (responseDone = '1') then
|
if (writeDone = '1') then
|
responseWriteReady <= '0';
|
responseReady <= '0';
|
state <= IDLE;
|
state <= IDLE;
|
else
|
else
|
responseWriteReady <= '1';
|
responseReady <= '1';
|
end if;
|
end if;
|
|
|
when others =>
|
when others =>
|
|
|
end case;
|
end case;
|
end if;
|
end if;
|
|
end if;
|
end process;
|
end process;
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
--
|
--
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
| Line 363... |
Line 454... |
tt_o=>requestTt,
|
tt_o=>requestTt,
|
dstId_o=>requestDstId,
|
dstId_o=>requestDstId,
|
srcId_o=>requestSrcId,
|
srcId_o=>requestSrcId,
|
tid_o=>requestTid,
|
tid_o=>requestTid,
|
address_o=>requestAddress,
|
address_o=>requestAddress,
|
length_o=>requestPayloadLength,
|
length_o=>requestLength,
|
select_o=>requestSelect,
|
select_o=>requestSelect,
|
done_i=>requestDone,
|
done_i=>requestDone,
|
slaveCyc_i=>inboundCyc,
|
slaveCyc_i=>inboundCyc,
|
slaveStb_i=>inboundStb,
|
slaveStb_i=>inboundStb,
|
slaveAdr_i=>inboundAdr,
|
slaveAdr_i=>inboundAdr,
|
slaveDat_i=>inboundDat,
|
slaveDat_i=>inboundDat,
|
slaveAck_o=>inboundAck);
|
slaveAck_o=>requestAck);
|
|
|
WriteClassInboundInst: WriteClassInbound
|
WriteClassInboundInst: WriteClassInbound
|
generic map(
|
generic map(
|
EXTENDED_ADDRESS=>EXTENDED_ADDRESS)
|
EXTENDED_ADDRESS=>EXTENDED_ADDRESS)
|
port map(
|
port map(
|
| Line 390... |
Line 481... |
srcId_o=>writeSrcId,
|
srcId_o=>writeSrcId,
|
tid_o=>writeTid,
|
tid_o=>writeTid,
|
address_o=>writeAddress,
|
address_o=>writeAddress,
|
length_o=>writeLength,
|
length_o=>writeLength,
|
select_o=>writeSelect,
|
select_o=>writeSelect,
|
payloadSetFirst_i=>writePayloadFirst,
|
payloadRead_i=>payloadUpdate,
|
payloadSetNext_i=>writePayloadNext,
|
payloadIndex_i=>payloadIndex,
|
payload_o=>writePayload,
|
payload_o=>writePayload,
|
done_i=>writeDone,
|
done_i=>writeDone,
|
slaveCyc_i=>inboundCyc_i,
|
slaveCyc_i=>inboundCyc,
|
slaveStb_i=>inboundStb_i,
|
slaveStb_i=>inboundStb,
|
slaveAdr_i=>inboundAdr_i,
|
slaveAdr_i=>inboundAdr,
|
slaveDat_i=>inboundDat_i,
|
slaveDat_i=>inboundDat,
|
slaveAck_o=>inboundAck_o);
|
slaveAck_o=>writeAck);
|
|
|
ResponseClassOutboundInst: ResponseClassOutbound
|
ResponseClassOutboundInst: ResponseClassOutbound
|
port map(
|
port map(
|
clk=>clk,
|
clk=>clk,
|
areset_n=>areset_n,
|
areset_n=>areset_n,
|
enable=>enable,
|
enable=>enable,
|
ready_i=>responseReady,
|
ready_i=>responseReady,
|
vc_i=>vc,
|
vc_i=>responseVc,
|
crf_i=>crf,
|
crf_i=>responseCrf,
|
prio_i=>prio,
|
prio_i=>responsePrio,
|
tt_i=>tt,
|
tt_i=>responseTt,
|
dstid_i=>srcid,
|
dstid_i=>responseDstId,
|
srcid_i=>dstid,
|
srcid_i=>responseSrcId,
|
tid_i=>tid,
|
tid_i=>responseTid,
|
error_i=>responseError,
|
error_i=>responseError,
|
payloadPresent_i=>responsePayloadPresent,
|
payloadPresent_i=>responsePayloadPresent,
|
payloadLength_i=>responsePayloadLength,
|
payloadLength_i=>requestLength,
|
payloadWrite_i=>responsePayloadWrite,
|
payloadWrite_i=>payloadUpdate,
|
payloadIndex_i=>responsePayloadIndex,
|
payloadIndex_i=>payloadIndex,
|
payload_i=>responsePayload,
|
payload_i=>responsePayload,
|
done_o=>responseDone,
|
done_o=>responseDone,
|
masterCyc_o=>outboundCyc,
|
masterCyc_o=>outboundCyc,
|
masterStb_o=>outboundStb,
|
masterStb_o=>outboundStb,
|
masterDat_o=>outboundDat,
|
masterDat_o=>outboundDat,
|
masterAck_i=>outboundAck);
|
masterAck_i=>outboundAck);
|
|
|
|
inboundAck <= requestAck or writeAck;
|
RioLogicalCommonInst: RioLogicalCommon
|
RioLogicalCommonInst: RioLogicalCommon
|
port map(
|
port map(
|
clk=>clk,
|
clk=>clk,
|
areset_n=>areset_n,
|
areset_n=>areset_n,
|
enable=>enable,
|
enable=>enable,
|
| Line 584... |
Line 676... |
tt_o : out std_logic_vector(1 downto 0);
|
tt_o : out std_logic_vector(1 downto 0);
|
dstId_o : out std_logic_vector(31 downto 0);
|
dstId_o : out std_logic_vector(31 downto 0);
|
srcId_o : out std_logic_vector(31 downto 0);
|
srcId_o : out std_logic_vector(31 downto 0);
|
tid_o : out std_logic_vector(7 downto 0);
|
tid_o : out std_logic_vector(7 downto 0);
|
address_o : out std_logic_vector(16*EXTENDED_ADDRESS+30 downto 0);
|
address_o : out std_logic_vector(16*EXTENDED_ADDRESS+30 downto 0);
|
length_o : out std_logic_vector(3 downto 0);
|
length_o : out std_logic_vector(4 downto 0);
|
select_o : out std_logic_vector(7 downto 0);
|
select_o : out std_logic_vector(7 downto 0);
|
done_i : in std_logic;
|
done_i : in std_logic;
|
|
|
slaveCyc_i : in std_logic;
|
slaveCyc_i : in std_logic;
|
slaveStb_i : in std_logic;
|
slaveStb_i : in std_logic;
|
| Line 620... |
Line 712... |
ready_o <= complete when (state = READY) else '0';
|
ready_o <= complete when (state = READY) else '0';
|
|
|
RequestClass: process(clk, areset_n)
|
RequestClass: process(clk, areset_n)
|
begin
|
begin
|
if (areset_n = '0') then
|
if (areset_n = '0') then
|
slaveAck <= '0';
|
state <= RECEIVE_PACKET;
|
|
|
|
rdsize <= (others=>'0');
|
|
wdptr <= '0';
|
|
|
|
slaveAck <= '0';
|
complete <= '0';
|
complete <= '0';
|
|
|
|
packetIndex <= 0;
|
|
|
vc_o <= '0';
|
vc_o <= '0';
|
crf_o <= '0';
|
crf_o <= '0';
|
prio_o <= "00";
|
prio_o <= "00";
|
tt_o <= "00";
|
tt_o <= "00";
|
|
dstId_o <= (others=>'0');
|
|
srcId_o <= (others=>'0');
|
|
tid_o <= (others=>'0');
|
address_o <= (others=>'0');
|
address_o <= (others=>'0');
|
|
|
rdsize <= (others=>'0');
|
|
wdptr <= '0';
|
|
|
|
packetIndex <= 0;
|
|
elsif (clk'event and clk = '1') then
|
elsif (clk'event and clk = '1') then
|
case state is
|
case state is
|
when RECEIVE_PACKET =>
|
when RECEIVE_PACKET =>
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
-- This state waits for a new REQUEST class packet, receives it
|
-- This state waits for a new REQUEST class packet, receives it
|
| Line 682... |
Line 778... |
complete <= '1';
|
complete <= '1';
|
when others =>
|
when others =>
|
-- There should be no more content in an NREAD.
|
-- There should be no more content in an NREAD.
|
-- Discard.
|
-- Discard.
|
end case;
|
end case;
|
end if;
|
|
slaveAck <= '1';
|
slaveAck <= '1';
|
end if;
|
end if;
|
|
end if;
|
else
|
else
|
slaveAck <= '0';
|
slaveAck <= '0';
|
end if;
|
end if;
|
else
|
else
|
if (complete = '1') then
|
if (complete = '1') then
|
| Line 721... |
Line 817... |
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
|
|
process(clk, areset_n)
|
process(clk, areset_n)
|
begin
|
begin
|
if (areset_n = '0') then
|
if (areset_n = '0') then
|
length_o <= 0;
|
length_o <= "00000";
|
select_o <= (others=>'0');
|
select_o <= (others=>'0');
|
elsif (clk'event and clk = '1') then
|
elsif (clk'event and clk = '1') then
|
if (complete = '1') then
|
if (complete = '1') then
|
if (wdptr = '0') then
|
if (wdptr = '0') then
|
case rdsize is
|
case rdsize is
|
when "0000" =>
|
when "0000" =>
|
length_o <= 0;
|
length_o <= "00000";
|
select_o <= "10000000";
|
select_o <= "10000000";
|
when "0001" =>
|
when "0001" =>
|
length_o <= 0;
|
length_o <= "00000";
|
select_o <= "01000000";
|
select_o <= "01000000";
|
when "0010" =>
|
when "0010" =>
|
length_o <= 0;
|
length_o <= "00000";
|
select_o <= "00100000";
|
select_o <= "00100000";
|
when "0011" =>
|
when "0011" =>
|
length_o <= 0;
|
length_o <= "00000";
|
select_o <= "00010000";
|
select_o <= "00010000";
|
when "0100" =>
|
when "0100" =>
|
length_o <= 0;
|
length_o <= "00000";
|
select_o <= "11000000";
|
select_o <= "11000000";
|
when "0101" =>
|
when "0101" =>
|
length_o <= 0;
|
length_o <= "00000";
|
select_o <= "11100000";
|
select_o <= "11100000";
|
when "0110" =>
|
when "0110" =>
|
length_o <= 0;
|
length_o <= "00000";
|
select_o <= "00110000";
|
select_o <= "00110000";
|
when "0111" =>
|
when "0111" =>
|
length_o <= 0;
|
length_o <= "00000";
|
select_o <= "11111000";
|
select_o <= "11111000";
|
when "1000" =>
|
when "1000" =>
|
length_o <= 0;
|
length_o <= "00000";
|
select_o <= "11110000";
|
select_o <= "11110000";
|
when "1001" =>
|
when "1001" =>
|
length_o <= 0;
|
length_o <= "00000";
|
select_o <= "11111100";
|
select_o <= "11111100";
|
when "1010" =>
|
when "1010" =>
|
length_o <= 0;
|
length_o <= "00000";
|
select_o <= "11111110";
|
select_o <= "11111110";
|
when "1011" =>
|
when "1011" =>
|
length_o <= 0;
|
length_o <= "00000";
|
select_o <= "11111111";
|
select_o <= "11111111";
|
when "1100" =>
|
when "1100" =>
|
length_o <= 3;
|
length_o <= "00011";
|
select_o <= "11111111";
|
select_o <= "11111111";
|
when "1101" =>
|
when "1101" =>
|
length_o <= 11;
|
length_o <= "01011";
|
select_o <= "11111111";
|
select_o <= "11111111";
|
when "1110" =>
|
when "1110" =>
|
length_o <= 19;
|
length_o <= "10011";
|
select_o <= "11111111";
|
select_o <= "11111111";
|
when others =>
|
when others =>
|
length_o <= 27;
|
length_o <= "11011";
|
select_o <= "11111111";
|
select_o <= "11111111";
|
end case;
|
end case;
|
else
|
else
|
case rdsize is
|
case rdsize is
|
when "0000" =>
|
when "0000" =>
|
length_o <= 0;
|
length_o <= "00000";
|
select_o <= "00001000";
|
select_o <= "00001000";
|
when "0001" =>
|
when "0001" =>
|
length_o <= 0;
|
length_o <= "00000";
|
select_o <= "00000100";
|
select_o <= "00000100";
|
when "0010" =>
|
when "0010" =>
|
length_o <= 0;
|
length_o <= "00000";
|
select_o <= "00000010";
|
select_o <= "00000010";
|
when "0011" =>
|
when "0011" =>
|
length_o <= 0;
|
length_o <= "00000";
|
select_o <= "00000001";
|
select_o <= "00000001";
|
when "0100" =>
|
when "0100" =>
|
length_o <= 0;
|
length_o <= "00000";
|
select_o <= "00001100";
|
select_o <= "00001100";
|
when "0101" =>
|
when "0101" =>
|
length_o <= 0;
|
length_o <= "00000";
|
select_o <= "00000111";
|
select_o <= "00000111";
|
when "0110" =>
|
when "0110" =>
|
length_o <= 0;
|
length_o <= "00000";
|
select_o <= "00000011";
|
select_o <= "00000011";
|
when "0111" =>
|
when "0111" =>
|
length_o <= 0;
|
length_o <= "00000";
|
select_o <= "00011111";
|
select_o <= "00011111";
|
when "1000" =>
|
when "1000" =>
|
length_o <= 0;
|
length_o <= "00000";
|
select_o <= "00001111";
|
select_o <= "00001111";
|
when "1001" =>
|
when "1001" =>
|
length_o <= 0;
|
length_o <= "00000";
|
select_o <= "00111111";
|
select_o <= "00111111";
|
when "1010" =>
|
when "1010" =>
|
length_o <= 0;
|
length_o <= "00000";
|
select_o <= "01111111";
|
select_o <= "01111111";
|
when "1011" =>
|
when "1011" =>
|
length_o <= 1;
|
length_o <= "00001";
|
select_o <= "11111111";
|
select_o <= "11111111";
|
when "1100" =>
|
when "1100" =>
|
length_o <= 7;
|
length_o <= "00111";
|
select_o <= "11111111";
|
select_o <= "11111111";
|
when "1101" =>
|
when "1101" =>
|
length_o <= 15;
|
length_o <= "01111";
|
select_o <= "11111111";
|
select_o <= "11111111";
|
when "1110" =>
|
when "1110" =>
|
length_o <= 23;
|
length_o <= "10111";
|
select_o <= "11111111";
|
select_o <= "11111111";
|
when others =>
|
when others =>
|
length_o <= 31;
|
length_o <= "11111";
|
select_o <= "11111111";
|
select_o <= "11111111";
|
end case;
|
end case;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
| Line 865... |
Line 961... |
tt_o : out std_logic_vector(1 downto 0);
|
tt_o : out std_logic_vector(1 downto 0);
|
dstId_o : out std_logic_vector(31 downto 0);
|
dstId_o : out std_logic_vector(31 downto 0);
|
srcId_o : out std_logic_vector(31 downto 0);
|
srcId_o : out std_logic_vector(31 downto 0);
|
tid_o : out std_logic_vector(7 downto 0);
|
tid_o : out std_logic_vector(7 downto 0);
|
address_o : out std_logic_vector(16*EXTENDED_ADDRESS+30 downto 0);
|
address_o : out std_logic_vector(16*EXTENDED_ADDRESS+30 downto 0);
|
length_o : out std_logic_vector(3 downto 0);
|
length_o : out std_logic_vector(4 downto 0);
|
select_o : out std_logic_vector(7 downto 0);
|
select_o : out std_logic_vector(7 downto 0);
|
payloadSetFirst_i : in std_logic;
|
payloadRead_i : in std_logic;
|
payloadSetNext_i : in std_logic;
|
payloadIndex_i : in std_logic_vector(4 downto 0);
|
payload_o : out std_logic_vector(31 downto 0);
|
payload_o : out std_logic_vector(63 downto 0);
|
done_i : in std_logic;
|
done_i : in std_logic;
|
|
|
slaveCyc_i : in std_logic;
|
slaveCyc_i : in std_logic;
|
slaveStb_i : in std_logic;
|
slaveStb_i : in std_logic;
|
slaveAdr_i : in std_logic_vector(7 downto 0);
|
slaveAdr_i : in std_logic_vector(7 downto 0);
|
| Line 910... |
Line 1006... |
|
|
signal slaveAck : std_logic;
|
signal slaveAck : std_logic;
|
signal complete : std_logic;
|
signal complete : std_logic;
|
|
|
signal packetIndex : natural range 0 to 68;
|
signal packetIndex : natural range 0 to 68;
|
signal requestData : std_logic_vector(31 downto 0);
|
|
|
|
signal payloadIndex : std_logic_vector(4 downto 0);
|
signal doubleWord : std_logic_vector(63 downto 16);
|
|
|
signal memoryWrite : std_logic;
|
signal memoryWrite : std_logic;
|
signal memoryAddress : std_logic_vector(4 downto 0);
|
signal memoryAddress : std_logic_vector(4 downto 0);
|
signal memoryDataIn : std_logic_vector(63 downto 0);
|
signal memoryDataIn : std_logic_vector(63 downto 0);
|
|
|
|
|
begin
|
begin
|
|
|
slaveAck_o <= slaveAck;
|
slaveAck_o <= slaveAck;
|
|
|
ready_o <= complete when (state = READY) else '0';
|
ready_o <= complete when (state = READY) else '0';
|
|
|
WriteClass: process(clk, areset_n)
|
WriteClass: process(clk, areset_n)
|
begin
|
begin
|
if (areset_n = '0') then
|
if (areset_n = '0') then
|
slaveAck <= '0';
|
state <= RECEIVE_PACKET;
|
|
|
complete <= '0';
|
|
|
|
vc_o <= '0';
|
|
crf_o <= '0';
|
|
prio_o <= "00";
|
|
tt_o <= "00";
|
|
tid_o <= (others=>'0');
|
|
|
|
address_o <= (others=>'0');
|
|
|
|
wdptr <= '0';
|
wdptr <= '0';
|
wrsize <= (others=>'0');
|
wrsize <= (others=>'0');
|
|
|
|
slaveAck <= '0';
|
|
complete <= '0';
|
|
|
packetIndex <= 0;
|
packetIndex <= 0;
|
|
doubleWord <= (others=>'0');
|
|
|
memoryWrite <= '0';
|
memoryWrite <= '0';
|
memoryAddress <= (others=>'0');
|
memoryAddress <= (others=>'0');
|
memoryDataIn <= (others=>'0');
|
memoryDataIn <= (others=>'0');
|
|
|
|
vc_o <= '0';
|
|
crf_o <= '0';
|
|
prio_o <= "00";
|
|
tt_o <= "00";
|
|
dstId_o <= (others=>'0');
|
|
srcId_o <= (others=>'0');
|
|
tid_o <= (others=>'0');
|
|
address_o <= (others=>'0');
|
elsif (clk'event and clk = '1') then
|
elsif (clk'event and clk = '1') then
|
case state is
|
case state is
|
when RECEIVE_PACKET =>
|
when RECEIVE_PACKET =>
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
-- This state waits for a new WRITE class packet, receives it
|
-- This state waits for a new WRITE class packet, receives it
|
| Line 1008... |
Line 1108... |
complete <= '1';
|
complete <= '1';
|
when others =>
|
when others =>
|
-- There should be no more content in an NWRITE request.
|
-- There should be no more content in an NWRITE request.
|
-- Discard.
|
-- Discard.
|
end case;
|
end case;
|
end if;
|
|
slaveAck <= '1';
|
slaveAck <= '1';
|
end if;
|
end if;
|
|
end if;
|
else
|
else
|
if (memoryWrite = '1') then
|
if (memoryWrite = '1') then
|
memoryAddress <= std_logic_vector(unsigned(memoryAddress) + 1);
|
memoryAddress <= std_logic_vector(unsigned(memoryAddress) + 1);
|
end if;
|
end if;
|
|
|
| Line 1053... |
Line 1153... |
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
|
|
process(clk, areset_n)
|
process(clk, areset_n)
|
begin
|
begin
|
if (areset_n = '0') then
|
if (areset_n = '0') then
|
length_o <= 0;
|
length_o <= "00000";
|
select_o <= (others=>'0');
|
select_o <= (others=>'0');
|
elsif (clk'event and clk = '1') then
|
elsif (clk'event and clk = '1') then
|
if (complete = '1') then
|
if (complete = '1') then
|
if (wdptr = '0') then
|
if (wdptr = '0') then
|
case wrsize is
|
case wrsize is
|
when "0000" =>
|
when "0000" =>
|
length_o <= 0;
|
length_o <= "00000";
|
select_o <= "10000000";
|
select_o <= "10000000";
|
when "0001" =>
|
when "0001" =>
|
length_o <= 0;
|
length_o <= "00000";
|
select_o <= "01000000";
|
select_o <= "01000000";
|
when "0010" =>
|
when "0010" =>
|
length_o <= 0;
|
length_o <= "00000";
|
select_o <= "00100000";
|
select_o <= "00100000";
|
when "0011" =>
|
when "0011" =>
|
length_o <= 0;
|
length_o <= "00000";
|
select_o <= "00010000";
|
select_o <= "00010000";
|
when "0100" =>
|
when "0100" =>
|
length_o <= 0;
|
length_o <= "00000";
|
select_o <= "11000000";
|
select_o <= "11000000";
|
when "0101" =>
|
when "0101" =>
|
length_o <= 0;
|
length_o <= "00000";
|
select_o <= "11100000";
|
select_o <= "11100000";
|
when "0110" =>
|
when "0110" =>
|
length_o <= 0;
|
length_o <= "00000";
|
select_o <= "00110000";
|
select_o <= "00110000";
|
when "0111" =>
|
when "0111" =>
|
length_o <= 0;
|
length_o <= "00000";
|
select_o <= "11111000";
|
select_o <= "11111000";
|
when "1000" =>
|
when "1000" =>
|
length_o <= 0;
|
length_o <= "00000";
|
select_o <= "11110000";
|
select_o <= "11110000";
|
when "1001" =>
|
when "1001" =>
|
length_o <= 0;
|
length_o <= "00000";
|
select_o <= "11111100";
|
select_o <= "11111100";
|
when "1010" =>
|
when "1010" =>
|
length_o <= 0;
|
length_o <= "00000";
|
select_o <= "11111110";
|
select_o <= "11111110";
|
when "1011" =>
|
when "1011" =>
|
length_o <= 0;
|
length_o <= "00000";
|
select_o <= "11111111";
|
select_o <= "11111111";
|
when others =>
|
when others =>
|
length_o <= memoryAddress;
|
length_o <= memoryAddress;
|
select_o <= "11111111";
|
select_o <= "11111111";
|
end case;
|
end case;
|
else
|
else
|
case wrsize is
|
case wrsize is
|
when "0000" =>
|
when "0000" =>
|
length_o <= 0;
|
length_o <= "00000";
|
select_o <= "00001000";
|
select_o <= "00001000";
|
when "0001" =>
|
when "0001" =>
|
length_o <= 0;
|
length_o <= "00000";
|
select_o <= "00000100";
|
select_o <= "00000100";
|
when "0010" =>
|
when "0010" =>
|
length_o <= 0;
|
length_o <= "00000";
|
select_o <= "00000010";
|
select_o <= "00000010";
|
when "0011" =>
|
when "0011" =>
|
length_o <= 0;
|
length_o <= "00000";
|
select_o <= "00000001";
|
select_o <= "00000001";
|
when "0100" =>
|
when "0100" =>
|
length_o <= 0;
|
length_o <= "00000";
|
select_o <= "00001100";
|
select_o <= "00001100";
|
when "0101" =>
|
when "0101" =>
|
length_o <= 0;
|
length_o <= "00000";
|
select_o <= "00000111";
|
select_o <= "00000111";
|
when "0110" =>
|
when "0110" =>
|
length_o <= 0;
|
length_o <= "00000";
|
select_o <= "00000011";
|
select_o <= "00000011";
|
when "0111" =>
|
when "0111" =>
|
length_o <= 0;
|
length_o <= "00000";
|
select_o <= "00011111";
|
select_o <= "00011111";
|
when "1000" =>
|
when "1000" =>
|
length_o <= 0;
|
length_o <= "00000";
|
select_o <= "00001111";
|
select_o <= "00001111";
|
when "1001" =>
|
when "1001" =>
|
length_o <= 0;
|
length_o <= "00000";
|
select_o <= "00111111";
|
select_o <= "00111111";
|
when "1010" =>
|
when "1010" =>
|
length_o <= 0;
|
length_o <= "00000";
|
select_o <= "01111111";
|
select_o <= "01111111";
|
when others =>
|
when others =>
|
length_o <= memoryAddress;
|
length_o <= memoryAddress;
|
select_o <= "11111111";
|
select_o <= "11111111";
|
end case;
|
end case;
|
| Line 1146... |
Line 1246... |
end process;
|
end process;
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- Payload content memory.
|
-- Payload content memory.
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
process(clk, areset_n)
|
|
begin
|
|
if (areset_n = '0') then
|
|
payloadIndex <= (others=>'0');
|
|
elsif (clk'event and clk = '1') then
|
|
if (payloadSetFirst_i = '1') then
|
|
payloadIndex <= (others=>'0');
|
|
elsif (payloadSetNext_i = '1') then
|
|
payloadIndex <= std_logic_vector(unsigned(payloadIndex) + 1);
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
PayloadMemory: MemorySimpleDualPort
|
PayloadMemory: MemorySimpleDualPort
|
generic map(ADDRESS_WIDTH=>5, DATA_WIDTH=>64)
|
generic map(ADDRESS_WIDTH=>5, DATA_WIDTH=>64)
|
port map(clkA_i=>clk,
|
port map(clkA_i=>clk,
|
enableA_i=>memoryWrite,
|
enableA_i=>memoryWrite,
|
addressA_i=>memoryAddress,
|
addressA_i=>memoryAddress,
|
dataA_i=>memoryDataIn,
|
dataA_i=>memoryDataIn,
|
clkB_i=>clk,
|
clkB_i=>clk,
|
enableB_i=>enable,
|
enableB_i=>payloadRead_i,
|
addressB_i=>payloadIndex,
|
addressB_i=>payloadIndex_i,
|
dataB_o=>payload_o);
|
dataB_o=>payload_o);
|
|
|
end architecture;
|
end architecture;
|
|
|
|
|
| Line 1201... |
Line 1289... |
dstid_i : in std_logic_vector(31 downto 0);
|
dstid_i : in std_logic_vector(31 downto 0);
|
srcid_i : in std_logic_vector(31 downto 0);
|
srcid_i : in std_logic_vector(31 downto 0);
|
tid_i : in std_logic_vector(7 downto 0);
|
tid_i : in std_logic_vector(7 downto 0);
|
error_i : in std_logic;
|
error_i : in std_logic;
|
payloadPresent_i : in std_logic;
|
payloadPresent_i : in std_logic;
|
payloadLength_i : in std_logic_vector(3 downto 0);
|
payloadLength_i : in std_logic_vector(4 downto 0);
|
payloadWrite_i : in std_logic;
|
payloadWrite_i : in std_logic;
|
payloadIndex_i : in std_logic_vector(3 downto 0);
|
payloadIndex_i : in std_logic_vector(4 downto 0);
|
payload_i : in std_logic_vector(31 downto 0);
|
payload_i : in std_logic_vector(63 downto 0);
|
done_o : out std_logic;
|
done_o : out std_logic;
|
|
|
masterCyc_o : out std_logic;
|
masterCyc_o : out std_logic;
|
masterStb_o : out std_logic;
|
masterStb_o : out std_logic;
|
masterDat_o : out std_logic_vector(31 downto 0);
|
masterDat_o : out std_logic_vector(31 downto 0);
|
| Line 1234... |
Line 1322... |
enableB_i : in std_logic;
|
enableB_i : in std_logic;
|
addressB_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
|
addressB_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
|
dataB_o : out std_logic_vector(DATA_WIDTH-1 downto 0));
|
dataB_o : out std_logic_vector(DATA_WIDTH-1 downto 0));
|
end component;
|
end component;
|
|
|
type StateType is (WAIT_PACKET,
|
signal header : std_logic_vector(31 downto 0);
|
READ_RESPONSE, WRITE_RESPONSE,
|
|
|
type StateType is (WAIT_PACKET, SEND_RESPONSE,
|
WAIT_COMPLETE, RESPONSE_DONE);
|
WAIT_COMPLETE, RESPONSE_DONE);
|
signal state : StateType;
|
signal state : StateType;
|
|
|
signal packetIndex : natural range 0 to 65;
|
signal packetIndex : natural range 0 to 68;
|
signal header : std_logic_vector(31 downto 0);
|
|
signal payload : std_logic_vector(63 downto 0);
|
signal responsePayloadIndex : std_logic_vector(4 downto 0);
|
signal payloadIndex : std_logic_vector(4 downto 0);
|
signal responsePayload : std_logic_vector(15 downto 0);
|
|
|
signal memoryEnable : std_logic;
|
signal memoryEnable : std_logic;
|
signal memoryAddress : std_logic_vector(4 downto 0);
|
signal memoryAddress : std_logic_vector(4 downto 0);
|
signal memoryDataRead : std_logic_vector(63 downto 0);
|
signal memoryDataRead : std_logic_vector(63 downto 0);
|
|
|
| Line 1255... |
Line 1344... |
header <= x"0000" & "000000" & vc_i & crf_i & prio_i & tt_i & x"d";
|
header <= x"0000" & "000000" & vc_i & crf_i & prio_i & tt_i & x"d";
|
|
|
Response: process(clk, areset_n)
|
Response: process(clk, areset_n)
|
begin
|
begin
|
if (areset_n = '0') then
|
if (areset_n = '0') then
|
masterCyc_o <= '0';
|
state <= WAIT_PACKET;
|
masterStb_o <= '0';
|
|
|
packetIndex <= 0;
|
|
|
|
responsePayloadIndex <= (others=>'0');
|
|
responsePayload <= (others=>'0');
|
|
|
memoryEnable <= '0';
|
memoryEnable <= '0';
|
memoryAddress <= (others=>'0');
|
memoryAddress <= (others=>'0');
|
|
|
payloadIndex <= (others=>'0');
|
|
done_o <= '0';
|
done_o <= '0';
|
|
|
state <= WAIT_PACKET;
|
masterCyc_o <= '0';
|
|
masterStb_o <= '0';
|
|
masterDat_o <= (others=>'0');
|
elsif (clk'event and clk = '1') then
|
elsif (clk'event and clk = '1') then
|
if (enable = '1') then
|
if (enable = '1') then
|
case state is
|
case state is
|
when WAIT_PACKET =>
|
when WAIT_PACKET =>
|
-------------------------------------------------------------------
|
-------------------------------------------------------------------
|
--
|
--
|
-------------------------------------------------------------------
|
-------------------------------------------------------------------
|
if (ready_i = '1') then
|
if (ready_i = '1') then
|
masterCyc_o <= '1';
|
masterCyc_o <= '1';
|
masterStb_o <= '1';
|
masterStb_o <= '1';
|
masterDat_o <= responseHeader;
|
masterDat_o <= header;
|
|
|
packetIndex <= 1;
|
packetIndex <= 1;
|
|
responsePayloadIndex <= (others=>'0');
|
|
|
memoryEnable <= '1';
|
memoryEnable <= '1';
|
memoryAddress <= (others=>'0');
|
memoryAddress <= (others=>'0');
|
|
|
payloadIndex <= (others=>'0');
|
|
state <= SEND_RESPONSE;
|
state <= SEND_RESPONSE;
|
end if;
|
end if;
|
|
|
when SEND_RESPONSE =>
|
when SEND_RESPONSE =>
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
| Line 1324... |
Line 1418... |
memoryAddress <= std_logic_vector(unsigned(memoryAddress) + 1);
|
memoryAddress <= std_logic_vector(unsigned(memoryAddress) + 1);
|
packetIndex <= packetIndex + 1;
|
packetIndex <= packetIndex + 1;
|
when 5 | 7 | 9 | 11 | 13 | 15 | 17 | 19 | 21 | 23 | 25 | 27 | 29 | 31 | 33 | 35 |
|
when 5 | 7 | 9 | 11 | 13 | 15 | 17 | 19 | 21 | 23 | 25 | 27 | 29 | 31 | 33 | 35 |
|
37 | 39 | 41 | 43 | 45 | 47 | 49 | 51 | 53 | 55 | 57 | 59 | 61 | 63 | 65 | 67 =>
|
37 | 39 | 41 | 43 | 45 | 47 | 49 | 51 | 53 | 55 | 57 | 59 | 61 | 63 | 65 | 67 =>
|
-- double-wordN(15:0) & double-wordN(63:48)
|
-- double-wordN(15:0) & double-wordN(63:48)
|
masterDat_o <= responsePayload & memoryDataRead(31 downto 16);
|
masterDat_o <= responsePayload & memoryDataRead(63 downto 48);
|
packetIndex <= packetIndex + 1;
|
packetIndex <= packetIndex + 1;
|
|
|
responsePayloadIndex <=
|
responsePayloadIndex <=
|
std_logic_vector(unsigned(responsePayloadIndex) + 1);
|
std_logic_vector(unsigned(responsePayloadIndex) + 1);
|
|
|
if (responsePayloadIndex = responsePayloadLength_i) then
|
if (responsePayloadIndex = payloadLength_i) then
|
state <= WAIT_COMPLETE;
|
state <= WAIT_COMPLETE;
|
else
|
else
|
packetIndex <= packetIndex + 1;
|
packetIndex <= packetIndex + 1;
|
end if;
|
end if;
|
when others =>
|
when others =>
|
