| Line 8... |
Line 8... |
-- Description
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-- Description
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-- Containing a bridge between a RapidIO network and a Wishbone bus. Packets
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-- Containing a bridge between a RapidIO network and a Wishbone bus. Packets
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-- NWRITE, NWRITER and NREAD are currently supported.
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-- NWRITE, NWRITER and NREAD are currently supported.
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--
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--
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-- To Do:
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-- To Do:
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-- - Move packet handlers to RioLogicalPackets.
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-- - Move packet handlers to RioLogicalPackets and make them symetrical.
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-- - Move component declarations to riocommon.
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-- - Add support for addressing to implementation defined config space by
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-- - Update the Maintenance handler to the new interface. It currently does not
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-- adding interface to top entity.
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-- compile.
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-- - Set the stb_o to '0' in between read accesses to conform better to a
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-- - Set the stb_o to '0' in between read accesses to conform better to a
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-- block transfer in the Wishbone standard.
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-- block transfer in the Wishbone standard.
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-- - Clean up cyc-signals, only stb-signals are needed (between
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-- - Clean up cyc-signals, only stb-signals are needed (between
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-- RioLogicalCommon and the packet handlers).
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-- RioLogicalCommon and the packet handlers).
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-- - Add support for the lock_o to be sure to transfer all the packet
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-- - Add support for the lock_o to be sure to transfer all the packet
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-- content atomically?
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-- content atomically?
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-- - Add support for EXTENDED_ADDRESS.
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-- - Add support for EXTENDED_ADDRESS.
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-- - Add support for addressing to implementation defined config space by
|
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-- adding interface to top entity.
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-- - Use the baseDeviceId when sending packets? Currently, all responses
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-- - Use the baseDeviceId when sending packets? Currently, all responses
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-- are sent with destination<->source exchanged so the baseDeviceId is not
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-- are sent with destination<->source exchanged so the baseDeviceId is not
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-- needed.
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-- needed.
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-- - Support inbound data with full bandwidth, not just half, applies to
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-- - Support inbound data with full bandwidth, not just half, applies to
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-- RioLogicalCommon and the packet handlers.
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-- RioLogicalCommon and the packet handlers.
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| Line 273... |
Line 270... |
signal crfInbound : std_logic;
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signal crfInbound : std_logic;
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signal prioInbound : std_logic_vector(1 downto 0);
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signal prioInbound : std_logic_vector(1 downto 0);
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signal ttInbound : std_logic_vector(1 downto 0);
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signal ttInbound : std_logic_vector(1 downto 0);
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signal dstIdInbound : std_logic_vector(31 downto 0);
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signal dstIdInbound : std_logic_vector(31 downto 0);
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signal srcIdInbound : std_logic_vector(31 downto 0);
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signal srcIdInbound : std_logic_vector(31 downto 0);
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signal sizeInbound : std_logic_vector(3 downto 0);
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signal tidInbound : std_logic_vector(7 downto 0);
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signal tidInbound : std_logic_vector(7 downto 0);
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signal offsetInbound : std_logic_vector(20 downto 0);
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signal offsetInbound : std_logic_vector(20 downto 0);
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signal wdptrInbound : std_logic;
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signal wdptrInbound : std_logic;
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signal payloadLengthInbound : std_logic_vector(3 downto 0);
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signal payloadLengthInbound : std_logic_vector(2 downto 0);
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signal payloadInbound : std_logic_vector(31 downto 0);
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signal payloadInbound : std_logic_vector(63 downto 0);
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|
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signal readResponseMaint : std_logic;
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signal readResponseMaint : std_logic;
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signal writeResponseMaint : std_logic;
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signal writeResponseMaint : std_logic;
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signal wdptrMaint : std_logic;
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signal statusMaint : std_logic_vector(3 downto 0);
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signal payloadLengthMaint : std_logic_vector(3 downto 0);
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signal payloadLengthMaint : std_logic_vector(2 downto 0);
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signal payloadIndexMaint : std_logic_vector(3 downto 0);
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signal payloadIndexMaint : std_logic_vector(2 downto 0);
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signal payloadMaint : std_logic_vector(31 downto 0);
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signal payloadMaint : std_logic_vector(63 downto 0);
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signal doneMaint : std_logic;
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signal doneMaint : std_logic;
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|
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signal payloadIndexOutbound : std_logic_vector(3 downto 0);
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signal payloadIndexOutbound : std_logic_vector(2 downto 0);
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signal doneOutbound : std_logic;
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signal doneOutbound : std_logic;
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|
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signal configStb : std_logic;
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signal configStb : std_logic;
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signal configWe : std_logic;
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signal configWe : std_logic;
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signal configAdr : std_logic_vector(21 downto 0);
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signal configAdr : std_logic_vector(21 downto 0);
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| Line 570... |
Line 568... |
crf_o=>crfInbound,
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crf_o=>crfInbound,
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prio_o=>prioInbound,
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prio_o=>prioInbound,
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tt_o=>ttInbound,
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tt_o=>ttInbound,
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dstid_o=>dstIdInbound,
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dstid_o=>dstIdInbound,
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srcid_o=>srcIdInbound,
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srcid_o=>srcIdInbound,
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size_o=>sizeInbound,
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status_o=>open,
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tid_o=>tidInbound,
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tid_o=>tidInbound,
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hop_o=>open,
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hop_o=>open,
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offset_o=>offsetInbound,
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offset_o=>offsetInbound,
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wdptr_o=>wdptrInbound,
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wdptr_o=>wdptrInbound,
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payloadLength_o=>payloadLengthInbound,
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payloadLength_o=>payloadLengthInbound,
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| Line 598... |
Line 598... |
crf_i=>crfInbound,
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crf_i=>crfInbound,
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prio_i=>prioInbound,
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prio_i=>prioInbound,
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tt_i=>ttInbound,
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tt_i=>ttInbound,
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dstid_i=>srcIdInbound,
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dstid_i=>srcIdInbound,
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srcid_i=>dstIdInbound,
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srcid_i=>dstIdInbound,
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status_i=>"0000",
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size_i=>(others=>'0'),
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status_i=>statusMaint,
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tid_i=>tidInbound,
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tid_i=>tidInbound,
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hop_i=>x"ff",
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hop_i=>x"ff",
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offset_i=>(others=>'0'),
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offset_i=>(others=>'0'),
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wdptr_i=>wdptrMaint,
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wdptr_i=>'0',
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payloadLength_i=>payloadLengthMaint,
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payloadLength_i=>payloadLengthMaint,
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payloadIndex_o=>payloadIndexOutbound,
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payloadIndex_o=>payloadIndexOutbound,
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payload_i=>payloadMaint,
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payload_i=>payloadMaint,
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done_o=>doneOutbound,
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done_o=>doneOutbound,
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outboundCyc_o=>outboundCyc(1),
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outboundCyc_o=>outboundCyc(1),
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| Line 617... |
Line 618... |
MaintenanceBridge: RioLogicalMaintenance
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MaintenanceBridge: RioLogicalMaintenance
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port map(
|
port map(
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clk=>clk, areset_n=>areset_n, enable=>enable,
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clk=>clk, areset_n=>areset_n, enable=>enable,
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readRequestReady_i=>readRequestInbound,
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readRequestReady_i=>readRequestInbound,
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writeRequestReady_i=>writeRequestInbound,
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writeRequestReady_i=>writeRequestInbound,
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size_i=>sizeInbound,
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offset_i=>offsetInbound,
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offset_i=>offsetInbound,
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wdptr_i=>wdptrInbound,
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wdptr_i=>wdptrInbound,
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payloadLength_i=>payloadLengthInbound,
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payloadLength_i=>payloadLengthInbound,
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payloadIndex_o=>payloadIndexMaint,
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payloadIndex_o=>payloadIndexMaint,
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payload_i=>payloadInbound,
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payload_i=>payloadInbound,
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done_o=>doneMaint,
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done_o=>doneMaint,
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readResponseReady_o=>readResponseMaint,
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readResponseReady_o=>readResponseMaint,
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writeResponseReady_o=>writeResponseMaint,
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writeResponseReady_o=>writeResponseMaint,
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wdptr_o=>wdptrMaint,
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status_o=>statusMaint,
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payloadLength_o=>payloadLengthMaint,
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payloadLength_o=>payloadLengthMaint,
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payloadIndex_i=>payloadIndexOutbound,
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payloadIndex_i=>payloadIndexOutbound,
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payload_o=>payloadMaint,
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payload_o=>payloadMaint,
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done_i=>doneOutbound,
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done_i=>doneOutbound,
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configStb_o=>configStb,
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configStb_o=>configStb,
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| Line 1149... |
Line 1151... |
|
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
|
--
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
architecture WriteClassInbound of WriteClassInbound is
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architecture WriteClassInbound of WriteClassInbound is
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component MemorySimpleDualPort
|
|
generic(
|
|
ADDRESS_WIDTH : natural := 1;
|
|
DATA_WIDTH : natural := 1);
|
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port(
|
|
clkA_i : in std_logic;
|
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enableA_i : in std_logic;
|
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addressA_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
|
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dataA_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
|
|
|
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clkB_i : in std_logic;
|
|
enableB_i : in std_logic;
|
|
addressB_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
|
|
dataB_o : out std_logic_vector(DATA_WIDTH-1 downto 0));
|
|
end component;
|
|
|
|
type StateType is (RECEIVE_PACKET, READY);
|
type StateType is (RECEIVE_PACKET, READY);
|
signal state : StateType;
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signal state : StateType;
|
|
|
signal wdptr : std_logic;
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signal wdptr : std_logic;
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signal wrsize : std_logic_vector(3 downto 0);
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signal wrsize : std_logic_vector(3 downto 0);
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| Line 1480... |
Line 1466... |
|
|
-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
|
--
|
--
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
architecture ResponseClassOutbound of ResponseClassOutbound is
|
architecture ResponseClassOutbound of ResponseClassOutbound is
|
component MemorySimpleDualPort
|
|
generic(
|
|
ADDRESS_WIDTH : natural := 1;
|
|
DATA_WIDTH : natural := 1);
|
|
port(
|
|
clkA_i : in std_logic;
|
|
enableA_i : in std_logic;
|
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addressA_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
|
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dataA_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
|
|
|
|
clkB_i : in std_logic;
|
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enableB_i : in std_logic;
|
|
addressB_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
|
|
dataB_o : out std_logic_vector(DATA_WIDTH-1 downto 0));
|
|
end component;
|
|
|
|
signal header : std_logic_vector(31 downto 0);
|
signal header : std_logic_vector(31 downto 0);
|
|
|
type StateType is (WAIT_PACKET, SEND_RESPONSE,
|
type StateType is (WAIT_PACKET, SEND_RESPONSE,
|
WAIT_COMPLETE, RESPONSE_DONE);
|
WAIT_COMPLETE, RESPONSE_DONE);
|
signal state : StateType;
|
signal state : StateType;
|
