?rev1line? |
?rev2line? |
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//*****************************************************************//
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// Syndrome Computation //
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// This block consists mainly of 12 cells. Each cell computes //
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// syndrome value Si, for i=0,...,11. //
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// At the end of received word block, all cells store the syndrome //
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// values, while SC block set its flag (errdetect) if one or more //
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// syndrome values are not zero. //
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// Ref.: "High-speed VLSI Architecture for Parallel Reed-Solomon //
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// Decoder", IEEE Trans. on VLSI, April 2003. //
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//*****************************************************************//
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module SCblock(recword, clock1, clock2, active_sc, reset, syndvalue0,
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syndvalue1, syndvalue2, syndvalue3, syndvalue4,
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syndvalue5, syndvalue6, syndvalue7, syndvalue8,
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syndvalue9, syndvalue10, syndvalue11, errdetect,
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en_sccell, evalsynd, holdsynd);
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input [4:0] recword;
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input clock1, clock2, active_sc, reset, evalsynd, holdsynd, en_sccell;
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output [4:0] syndvalue0, syndvalue1, syndvalue2, syndvalue3, syndvalue4,
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syndvalue5, syndvalue6, syndvalue7, syndvalue8, syndvalue9,
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syndvalue10, syndvalue11;
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output errdetect;
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reg errdetect;
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reg [1:0] state, nxt_state;
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parameter [1:0] st0=0, st1=1, st2=2;
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always@(state or active_sc or evalsynd)
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begin
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case(state)
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st0: begin
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if(active_sc)
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nxt_state <= st1;
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else
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nxt_state <= st0;
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end
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st1: begin
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if(evalsynd)
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nxt_state <= st2;
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else
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nxt_state <= st1;
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end
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st2: nxt_state <= st0;
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default: nxt_state <= st0;
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endcase
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end
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always@(posedge clock2 or negedge reset)
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begin
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if(~reset)
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state <= st0;
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else
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state <= nxt_state;
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end
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always@(state or syndvalue0 or syndvalue1 or syndvalue2 or syndvalue3 or
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syndvalue4 or syndvalue5 or syndvalue6 or syndvalue7 or syndvalue8 or
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syndvalue9 or syndvalue10 or syndvalue11)
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begin
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case(state)
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st0: errdetect <= 0;
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st1: errdetect <= 0;
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st2: begin
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if (syndvalue0 || syndvalue1 || syndvalue2 || syndvalue3 ||
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syndvalue4 || syndvalue5 || syndvalue6 || syndvalue7 ||
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syndvalue8 || syndvalue9 || syndvalue10 || syndvalue11)
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errdetect <= 1;
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else
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errdetect <= 0;
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end
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default:errdetect = 0;
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endcase
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end
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syndcell_0 cell_0(recword, clock1, en_sccell, holdsynd, syndvalue0);
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syndcell_1 cell_1(recword, clock1, en_sccell, holdsynd, syndvalue1);
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syndcell_2 cell_2(recword, clock1, en_sccell, holdsynd, syndvalue2);
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syndcell_3 cell_3(recword, clock1, en_sccell, holdsynd, syndvalue3);
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syndcell_4 cell_4(recword, clock1, en_sccell, holdsynd, syndvalue4);
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syndcell_5 cell_5(recword, clock1, en_sccell, holdsynd, syndvalue5);
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syndcell_6 cell_6(recword, clock1, en_sccell, holdsynd, syndvalue6);
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syndcell_7 cell_7(recword, clock1, en_sccell, holdsynd, syndvalue7);
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syndcell_8 cell_8(recword, clock1, en_sccell, holdsynd, syndvalue8);
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syndcell_9 cell_9(recword, clock1, en_sccell, holdsynd, syndvalue9);
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syndcell_10 cell_10(recword, clock1, en_sccell, holdsynd, syndvalue10);
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syndcell_11 cell_11(recword, clock1, en_sccell, holdsynd, syndvalue11);
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endmodule
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//*****************************/
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// Syndrome Computation Cells //
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//****************************//
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//**************************************************//
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//syndcell_0 computes R(alpha^19) for 31 clock cycles//
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//**************************************************//
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module syndcell_0(recword, clock, enable, hold, synvalue0);
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input [0:4] recword;
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input clock;
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input enable, hold;
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output [0:4] synvalue0;
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wire [0:4] outreg;
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wire [0:4] outadder;
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wire [0:4] outmult;
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//multiply recword with constant alpha^19
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assign outmult[0] = outreg[3] ^ outreg[4];
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assign outmult[1] = outreg[0] ^ outreg[4];
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assign outmult[2] = (outreg[0] ^ outreg[1]) ^ (outreg[3] ^ outreg[4]);
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assign outmult[3] = (outreg[1] ^ outreg[2]) ^ outreg[4];
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assign outmult[4] = outreg[2] ^ outreg[3];
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register5_wlh register5bit(outadder, outreg, enable, hold, clock);
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gfadder adder(recword, outmult, outadder);
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assign synvalue0 = outreg;
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endmodule
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//**************************************************//
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//syndcell_1 computes R(alpha^20) for 31 clock cycles//
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//**************************************************//
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module syndcell_1(recword, clock, enable, hold, synvalue1);
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input [0:4] recword;
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input clock;
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input enable, hold;
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output [0:4] synvalue1;
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wire [0:4] outreg;
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wire [0:4] outadder;
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wire [0:4] outmult;
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//multiply recword with constant alpha^20
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assign outmult[0] = outreg[2] ^ outreg[3];
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assign outmult[1] = outreg[3] ^ outreg[4];
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assign outmult[2] = (outreg[0] ^ outreg[4]) ^ (outreg[2] ^ outreg[3]);
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assign outmult[3] = (outreg[0] ^ outreg[1]) ^ (outreg[3] ^ outreg[4]);
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assign outmult[4] = (outreg[1] ^ outreg[2]) ^ outreg[4];
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register5_wlh register5bit(outadder, outreg, enable, hold, clock);
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gfadder adder(recword, outmult, outadder);
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assign synvalue1 = outreg;
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endmodule
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//**************************************************//
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//syndcell_2 computes R(alpha^21) for 31 clock cycles//
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//**************************************************//
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module syndcell_2(recword, clock, enable, hold, synvalue2);
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input [0:4] recword;
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input clock;
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input enable, hold;
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output [0:4] synvalue2;
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wire [0:4] outreg;
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wire [0:4] outadder;
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wire [0:4] outmult;
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//multiply recword with constant alpha^21
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assign outmult[0] = (outreg[1] ^ outreg[2]) ^ outreg[4];
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assign outmult[1] = outreg[2] ^ outreg[3];
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assign outmult[2] = (outreg[1] ^ outreg[2]) ^ outreg[3];
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assign outmult[3] = (outreg[0] ^ outreg[2]) ^ (outreg[3] ^ outreg[4]);
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assign outmult[4] = (outreg[0] ^ outreg[1]) ^ (outreg[3] ^ outreg[4]);
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register5_wlh register5bit(outadder, outreg, enable, hold, clock);
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gfadder adder(recword, outmult, outadder);
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assign synvalue2 = outreg;
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endmodule
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//**************************************************//
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//syndcell_3 computes R(alpha^22) for 31 clock cycles//
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//**************************************************//
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module syndcell_3(recword, clock, enable, hold, synvalue3);
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input [0:4] recword;
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input clock;
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input enable, hold;
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output [0:4] synvalue3;
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wire [0:4] outreg;
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wire [0:4] outadder;
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wire [0:4] outmult;
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//multiply recword with constant alpha^22
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assign outmult[0] = (outreg[0] ^ outreg[1]) ^ (outreg[3] ^ outreg[4]);
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assign outmult[1] = (outreg[1] ^ outreg[2]) ^ outreg[4];
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assign outmult[2] = (outreg[0] ^ outreg[1]) ^ (outreg[2] ^ outreg[4]);
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assign outmult[3] = (outreg[1] ^ outreg[2]) ^ outreg[3];
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assign outmult[4] = (outreg[0] ^ outreg[2]) ^ (outreg[3] ^ outreg[4]);
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register5_wlh register5bit(outadder, outreg, enable, hold, clock);
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gfadder adder(recword, outmult, outadder);
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assign synvalue3 = outreg;
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endmodule
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//***************************************************//
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//syndcell_4 computes R(alpha^23) for 31 clock cycles//
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//**************************************************//
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module syndcell_4(recword, clock, enable, hold, synvalue4);
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input [0:4] recword;
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input clock;
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input enable, hold;
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output [0:4] synvalue4;
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wire [0:4] outreg;
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wire [0:4] outadder;
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wire [0:4] outmult;
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//multiply recword with constant alpha^23
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assign outmult[0] = (outreg[0] ^ outreg[2]) ^ (outreg[3] ^ outreg[4]);
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assign outmult[1] = (outreg[0] ^ outreg[1]) ^ (outreg[3] ^ outreg[4]);
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assign outmult[2] = (outreg[0] ^ outreg[1]) ^ outreg[3];
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assign outmult[3] = (outreg[0] ^ outreg[1]) ^ (outreg[2] ^ outreg[4]);
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assign outmult[4] = (outreg[1] ^ outreg[2]) ^ outreg[3];
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register5_wlh register5bit(outadder, outreg, enable, hold, clock);
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gfadder adder(recword, outmult, outadder);
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assign synvalue4 = outreg;
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endmodule
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//***************************************************//
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//syndcell_5 computes R(alpha^24) for 31 clock cycles//
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//***************************************************//
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module syndcell_5(recword, clock, enable, hold, synvalue5);
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input [0:4] recword;
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input clock;
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input enable, hold;
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output [0:4] synvalue5;
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wire [0:4] outreg;
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wire [0:4] outadder;
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wire [0:4] outmult;
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//multiply recword with constant alpha^24
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assign outmult[0] = (outreg[1] ^ outreg[2]) ^ outreg[3];
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assign outmult[1] = (outreg[0] ^ outreg[2]) ^ (outreg[3] ^ outreg[4]);
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assign outmult[2] = (outreg[0] ^ outreg[2]) ^ outreg[4];
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assign outmult[3] = (outreg[0] ^ outreg[1]) ^ outreg[3];
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assign outmult[4] = (outreg[0] ^ outreg[1]) ^ (outreg[2] ^ outreg[4]);
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register5_wlh register5bit(outadder, outreg, enable, hold, clock);
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gfadder adder(recword, outmult, outadder);
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assign synvalue5 = outreg;
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endmodule
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//***************************************************//
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//syndcell_6 computes R(alpha^25) for 31 clock cycles//
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//***************************************************//
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module syndcell_6(recword, clock, enable, hold, synvalue6);
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input [0:4] recword;
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input clock;
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input enable, hold;
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output [0:4] synvalue6;
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wire [0:4] outreg;
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wire [0:4] outadder;
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wire [0:4] outmult;
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//multiply recword with constant alpha^25
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assign outmult[0] = (outreg[0] ^ outreg[1]) ^ (outreg[2] ^ outreg[4]);
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assign outmult[1] = (outreg[1] ^ outreg[2]) ^ outreg[3];
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assign outmult[2] = outreg[1] ^ outreg[3];
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assign outmult[3] = (outreg[0] ^ outreg[2]) ^ outreg[4];
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assign outmult[4] = (outreg[0] ^ outreg[1]) ^ outreg[3];
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register5_wlh register5bit(outadder, outreg, enable, hold, clock);
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gfadder adder(recword, outmult, outadder);
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assign synvalue6 = outreg;
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endmodule
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//***************************************************//
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//syndcell_7 computes R(alpha^26) for 31 clock cycles//
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//***************************************************//
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module syndcell_7(recword, clock, enable, hold, synvalue7);
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input [0:4] recword;
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input clock;
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input enable, hold;
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output [0:4] synvalue7;
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wire [0:4] outreg;
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wire [0:4] outadder;
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wire [0:4] outmult;
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//multiply recword with constant alpha^26
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assign outmult[0] = (outreg[0] ^ outreg[1]) ^ outreg[3];
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assign outmult[1] = (outreg[0] ^ outreg[1]) ^ (outreg[2] ^ outreg[4]);
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assign outmult[2] = outreg[0] ^ outreg[2];
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assign outmult[3] = outreg[1] ^ outreg[3];
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assign outmult[4] = (outreg[0] ^ outreg[2]) ^ outreg[4];
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register5_wlh register5bit(outadder, outreg, enable, hold, clock);
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gfadder adder(recword, outmult, outadder);
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assign synvalue7 = outreg;
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endmodule
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//***************************************************//
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//syndcell_8 computes R(alpha^27) for 31 clock cycles//
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//***************************************************//
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module syndcell_8(recword, clock, enable, hold, synvalue8);
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input [0:4] recword;
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input clock;
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input enable, hold;
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output [0:4] synvalue8;
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wire [0:4] outreg;
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wire [0:4] outadder;
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wire [0:4] outmult;
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//multiply recword with constant alpha^27
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assign outmult[0] = (outreg[0] ^ outreg[2]) ^ outreg[4];
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assign outmult[1] = (outreg[0] ^ outreg[1]) ^ outreg[3];
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assign outmult[2] = outreg[1];
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assign outmult[3] = outreg[0] ^ outreg[2];
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assign outmult[4] = outreg[1] ^ outreg[3];
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register5_wlh register5bit(outadder, outreg, enable, hold, clock);
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gfadder adder(recword, outmult, outadder);
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assign synvalue8 = outreg;
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endmodule
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//***************************************************//
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//syndcell_9 computes R(alpha^28) for 31 clock cycles//
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//***************************************************//
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module syndcell_9(recword, clock, enable, hold, synvalue9);
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input [0:4] recword;
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input clock;
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input enable, hold;
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output [0:4] synvalue9;
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wire [0:4] outreg;
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wire [0:4] outadder;
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wire [0:4] outmult;
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//multiply recword with constant alpha^28
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assign outmult[0] = outreg[1] ^ outreg[3];
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assign outmult[1] = (outreg[0] ^ outreg[2]) ^ outreg[4];
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assign outmult[2] = outreg[0];
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assign outmult[3] = outreg[1];
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assign outmult[4] = outreg[0] ^ outreg[2];
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register5_wlh register5bit(outadder, outreg, enable, hold, clock);
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gfadder adder(recword, outmult, outadder);
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assign synvalue9 = outreg;
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endmodule
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//****************************************************//
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//syndcell_10 computes R(alpha^29) for 31 clock cycles//
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//****************************************************//
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module syndcell_10(recword, clock, enable, hold, synvalue10);
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input [0:4] recword;
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input clock;
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input enable, hold;
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output [0:4] synvalue10;
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wire [0:4] outreg;
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wire [0:4] outadder;
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wire [0:4] outmult;
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//multiply recword with constant alpha^29
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assign outmult[0] = outreg[0] ^ outreg[2];
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assign outmult[1] = outreg[1] ^ outreg[3];
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assign outmult[2] = outreg[4];
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assign outmult[3] = outreg[0];
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assign outmult[4] = outreg[1];
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register5_wlh register5bit(outadder, outreg, enable, hold, clock);
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gfadder adder(recword, outmult, outadder);
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assign synvalue10 = outreg;
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endmodule
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//****************************************************//
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//syndcell_11 computes R(alpha^30) for 31 clock cycles//
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//****************************************************//
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module syndcell_11(recword, clock, enable, hold, synvalue11);
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input [0:4] recword;
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input clock;
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input enable, hold;
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output [0:4] synvalue11;
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wire [0:4] outreg;
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wire [0:4] outadder;
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wire [0:4] outmult;
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//multiply recword with constant alpha^30
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assign outmult[0] = outreg[1];
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assign outmult[1] = outreg[0] ^ outreg[2];
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assign outmult[2] = outreg[3];
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assign outmult[3] = outreg[4];
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assign outmult[4] = outreg[0];
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register5_wlh register5bit(outadder, outreg, enable, hold, clock);
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gfadder adder(recword, outmult, outadder);
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assign synvalue11 = outreg;
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endmodule
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