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//******************************************************//
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// This file contains definition of common modules used //
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// by higher level modules in RS Decoder //
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//******************************************************//
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//*************************//
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// Multiplexer 2 to 1 5bit //
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//*************************//
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module mux2_to_1(in1, in2 , out, sel);
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input [4:0] in1, in2;
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input sel;
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output [4:0] out;
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reg [4:0] out;
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always@(sel or in1 or in2)
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begin
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case(sel)
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0 : out = in1;
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1 : out = in2;
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default: out = in1;
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endcase
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end
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endmodule
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//**********************************************//
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//Register 5 bit with synchronous load and hold //
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//**********************************************//
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module register5_wlh(datain, dataout, load, hold, clock);
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input [4:0] datain;
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input load, hold;
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input clock;
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output [4:0] dataout;
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reg [4:0] out;
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always @(posedge clock)
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begin
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if(load)
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out <= datain;
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else if(hold)
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out <= out;
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else
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out <= 5'b0;
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end
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assign dataout = out;
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endmodule
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//**************************************//
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// Register 5 bit with synchronous load //
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//**************************************//
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module register5_wl(datain, dataout, clock, load);
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input [4:0] datain;
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output [4:0] dataout;
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input clock, load;
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reg [4:0] dataout;
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always@(posedge clock)
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begin
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if(load)
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dataout <= datain;
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else
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dataout <= 5'b0;
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end
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endmodule
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//**************//
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//GF(2^5) Adder //
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//**************//
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module gfadder(in1, in2, out);
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input [0:4] in1, in2;
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output [0:4] out;
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assign out[4] = in1[4] ^ in2[4];
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assign out[3] = in1[3] ^ in2[3];
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assign out[2] = in1[2] ^ in2[2];
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assign out[1] = in1[1] ^ in2[1];
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assign out[0] = in1[0] ^ in2[0];
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endmodule
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//*********************************************//
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// GF(2^5) parallel multiplier is based on //
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// the design proposed by M. Anwar Hasan & //
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// A. Reyhani-Masoleh in their paper entitled //
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// "Low Complexity Bit Parallel Architectures //
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// for Polynomial Basis Multiplication over //
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// GF(2^m)" published in IEEE Transactions On //
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// Computer August 2004. //
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//*********************************************//
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module lcpmult(in1, in2, out);
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input [0:4] in1, in2; //in1[4] & in2[4] is MSB
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output [0:4] out;
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wire [4:0] intvald; //intermediate val d
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wire [3:0] intvale; //intermediate val e
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wire intvale_0ax; //intermediate val e'[0]
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assign intvald[0] = in1[0] & in2[0];
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assign intvald[1] = (in1[1] & in2[0]) ^ (in1[0] & in2[1]);
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assign intvald[2] = (in1[2] & in2[0]) ^ ((in1[1] & in2[1]) ^ (in1[0] & in2[2]));
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assign intvald[3] = ((in1[3] & in2[0]) ^ (in1[2] & in2[1])) ^ ((in1[1] & in2[2]) ^ (in1[0] & in2[3]));
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assign intvald[4] = (((in1[4] & in2[0]) ^ (in1[3] & in2[1])) ^ (in1[2] & in2[2]))
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^ ((in1[1] & in2[3]) ^ (in1[0] & in2[4]));
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assign intvale[0] = ((in1[4] & in2[1]) ^ (in1[3] & in2[2])) ^ ((in1[2] & in2[3]) ^ (in1[1] & in2[4]));
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assign intvale[1] = ((in1[4] & in2[2]) ^ (in1[3] & in2[3])) ^ (in1[2] & in2[4]);
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assign intvale[2] = (in1[4] & in2[3]) ^ (in1[3] & in2[4]);
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assign intvale[3] = in1[4] & in2[4];
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assign intvale_0ax = (intvale[0] ^ intvale[3]);
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assign out[0] = intvald[0] ^ intvale_0ax;
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assign out[1] = intvald[1] ^ intvale[1];
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assign out[2] = (intvald[2] ^ intvale[2]) ^ intvale_0ax;
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assign out[3] = (intvald[3] ^ intvale[1]) ^ intvale[3];
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assign out[4] = intvald[4] ^ intvale[2];
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endmodule
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