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//***************************************************************//
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// Chien Search and Error Evaluator (CSEE) block find //
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// error location (Xi) while determine its error magnitude (Yi). //
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// This CSEE block implement Chien search algorithm to find //
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// location of an error and Fourney Formula to compute the error //
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// error value. Error value will be outputted serially and has //
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// to be synchronous with output of FIFO Register. //
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//***************************************************************//
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module CSEEblock(lambda0, lambda1, lambda2, lambda3, lambda4,
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lambda5, lambda6, homega0, homega1, homega2,
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homega3, homega4, homega5, errorvalue, clock1,
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clock2, active_csee, reset, lastdataout, evalerror,
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en_outfifo, rootcntr);
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input [4:0] lambda0, lambda1, lambda2, lambda3, lambda4,
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lambda5, lambda6;
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input [4:0] homega0, homega1, homega2, homega3, homega4, homega5;
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input clock1, clock2, active_csee, reset;
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input lastdataout, evalerror, en_outfifo;
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output [4:0] errorvalue;
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output [2:0] rootcntr;
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wire [4:0] cs0_out, cs1_out, cs2_out, cs3_out, cs4_out, cs5_out,
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cs6_out;
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wire [4:0] fn0_out, fn1_out, fn2_out, fn3_out, fn4_out, fn5_out;
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wire [4:0] oddlambda, evenlambda, lambdaval;
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wire [4:0] omegaval, fourney_out, inv_oddlambda;
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wire zerodetect;
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wire [4:0] andtree_out;
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reg load;
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reg enrootcnt;
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reg [2:0] rootcntr;
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parameter st0=0, st1=1;
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reg state, nxt_state;
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//*****//
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// FSM //
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//*****//
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always@(posedge clock2 or negedge reset)
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begin
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if(~reset)
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state = st0;
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else
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state = nxt_state;
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end
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always@(state or active_csee or lastdataout)
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begin
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case(state)
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st0 : begin
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if(active_csee)
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nxt_state = st1;
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else
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nxt_state = st0;
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end
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st1 : begin
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if(lastdataout)
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nxt_state = st0;
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else
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nxt_state = st1;
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end
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default: nxt_state = st0;
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endcase
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end
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always@(state)
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begin
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case(state)
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st0 : begin
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load = 0;
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enrootcnt = 0;
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end
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st1 : begin
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load = 1;
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enrootcnt = 1;
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end
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default: begin
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load = 0;
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enrootcnt = 0;
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end
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endcase
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end
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//********************************//
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// Counter for roots of lambda(x) //
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// with synchronous hold //
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//********************************//
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always@(posedge clock2)
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begin
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if(enrootcnt)
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begin
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if(zerodetect)
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rootcntr <= rootcntr + 1;
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else
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rootcntr <= rootcntr;
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end
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else
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rootcntr <= 3'b0;
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end
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//*******************//
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// Chien Seach block //
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//*******************//
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degree0_cell cs0_cell(lambda0, cs0_out, clock1, load, evalerror);
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degree1_cell cs1_cell(lambda1, cs1_out, clock1, load, evalerror);
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degree2_cell cs2_cell(lambda2, cs2_out, clock1, load, evalerror);
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degree3_cell cs3_cell(lambda3, cs3_out, clock1, load, evalerror);
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degree4_cell cs4_cell(lambda4, cs4_out, clock1, load, evalerror);
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degree5_cell cs5_cell(lambda5, cs5_out, clock1, load, evalerror);
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degree6_cell cs6_cell(lambda6, cs6_out, clock1, load, evalerror);
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assign oddlambda = cs1_out ^ cs3_out ^ cs5_out;
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assign evenlambda = (cs0_out ^ cs2_out) ^ (cs4_out ^ cs6_out);
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assign lambdaval = oddlambda ^ evenlambda;
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//*****************************************//
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// Error Evaluator (Fourney Formula) block //
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//*****************************************//
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degree0_cell fn0_cell(homega0, fn0_out, clock1, load, evalerror);
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degree1_cell fn1_cell(homega1, fn1_out, clock1, load, evalerror);
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degree2_cell fn2_cell(homega2, fn2_out, clock1, load, evalerror);
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degree3_cell fn3_cell(homega3, fn3_out, clock1, load, evalerror);
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degree4_cell fn4_cell(homega4, fn4_out, clock1, load, evalerror);
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degree5_cell fn5_cell(homega5, fn5_out, clock1, load, evalerror);
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assign omegaval = (fn0_out ^ fn1_out) ^ (fn2_out ^ fn3_out) ^
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(fn4_out ^ fn5_out);
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inverscomb invers(oddlambda, inv_oddlambda);
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lcpmult multiplier(inv_oddlambda, omegaval, fourney_out);
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//*****************************//
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// Zero detect and error value //
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//*****************************//
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assign zerodetect = ~((lambdaval[0]|lambdaval[1]) |
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(lambdaval[2]|lambdaval[3]) | lambdaval[4]);
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assign andtree_out[0] = fourney_out[0] & zerodetect;
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assign andtree_out[1] = fourney_out[1] & zerodetect;
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assign andtree_out[2] = fourney_out[2] & zerodetect;
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assign andtree_out[3] = fourney_out[3] & zerodetect;
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assign andtree_out[4] = fourney_out[4] & zerodetect;
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//assign errorvalue = andtree_out;
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register5_wl erroreg(andtree_out, errorvalue, clock2, en_outfifo);
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endmodule
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//******************************************************//
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// Modul-modul chien search cell dibentuk dgn perkalian //
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//***********************************************//
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// Module for terms whose degree is zero //
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//***********************************************//
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module degree0_cell(in, out, clock, load, compute);
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input [4:0] in;
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output [4:0] out;
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input clock, compute, load;
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wire [4:0] outmux, outreg;
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register5_wl register(outmux, outreg, clock, load);
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mux2_to_1 multiplex(in, outreg, outmux, compute);
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assign out = outreg;
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endmodule
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//********************************************************//
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// Module that computes term with degree one. //
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// Constructed by a variable-constant multiplier with //
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// alpha^1 as constant. //
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//********************************************************//
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module degree1_cell(in, out, clock, load, compute);
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input [4:0] in;
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output [4:0] out;
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input clock, load, compute;
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wire [4:0] outmux;
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wire [0:4] outmult, outreg;
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register5_wl register(outmux, outreg, clock, load);
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mux2_to_1 multiplexer(in, outmult, outmux, compute);
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//Multipy variable-alpha^1
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assign outmult[0] = outreg[4];
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assign outmult[1] = outreg[0];
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assign outmult[2] = outreg[1] ^ outreg[4];
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assign outmult[3] = outreg[2];
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assign outmult[4] = outreg[3];
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assign out = outreg;
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endmodule
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//********************************************************//
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// Module that computes term with degree two.
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// Constructed by a variable-constant multiplier with
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// alpha^2 as constant. //
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//********************************************************//
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module degree2_cell(in, out, clock, load, compute);
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input [4:0] in;
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output [4:0] out;
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input clock, load, compute;
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wire [4:0] outmux;
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wire [0:4] outmult, outreg;
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register5_wl register(outmux, outreg, clock, load);
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mux2_to_1 multiplexer(in, outmult, outmux, compute);
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//Multipy variable-alpha^2
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assign outmult[0] = outreg[3];
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assign outmult[1] = outreg[4];
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assign outmult[2] = outreg[0] ^ outreg[3];
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assign outmult[3] = outreg[1] ^ outreg[4];
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assign outmult[4] = outreg[2];
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assign out = outreg;
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endmodule
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//********************************************************//
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// Module that computes term with degree three. //
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// Constructed by a variable-constant multiplier with //
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// alpha^3 as constant. //
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//********************************************************//
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module degree3_cell(in, out, clock, load, compute);
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input [4:0] in;
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output [4:0] out;
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input clock, load, compute;
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wire [4:0] outmux;
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wire [0:4] outmult, outreg;
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register5_wl register(outmux, outreg, clock, load);
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mux2_to_1 multiplexer(in, outmult, outmux, compute);
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//Multipy variable-alpha^3
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assign outmult[0] = outreg[2];
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assign outmult[1] = outreg[3];
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assign outmult[2] = outreg[2] ^ outreg[4];
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assign outmult[3] = outreg[0] ^ outreg[3];
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assign outmult[4] = outreg[1] ^ outreg[4];
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assign out = outreg;
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endmodule
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//********************************************************//
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// Module that computes term with degree four. //
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// Constructed by a variable-constant multiplier with //
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// alpha^4 as constant. //
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//********************************************************//
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module degree4_cell(in, out, clock, load, compute);
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input [4:0] in;
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output [4:0] out;
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input clock, load, compute;
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wire [4:0] outmux;
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wire [0:4] outmult, outreg;
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register5_wl register(outmux, outreg, clock, load);
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mux2_to_1 multiplexer(in, outmult, outmux, compute);
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//Multipy variable-alpha^4
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assign outmult[0] = outreg[1] ^ outreg[4];
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assign outmult[1] = outreg[2];
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assign outmult[2] = outreg[1] ^ outreg[3] ^ outreg[4];
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assign outmult[3] = outreg[2] ^ outreg[4];
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assign outmult[4] = outreg[0] ^ outreg[3];
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assign out = outreg;
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endmodule
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//********************************************************//
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// Module that computes term with degree five. //
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// Constructed by a variable-constant multiplier with //
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// alpha^5 as constant. //
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//********************************************************//
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module degree5_cell(in, out, clock, load, compute);
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input [4:0] in;
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output [4:0] out;
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input clock, load, compute;
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wire [4:0] outmux;
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wire [0:4] outmult, outreg;
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register5_wl register(outmux, outreg, clock, load);
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mux2_to_1 multiplexer(in, outmult, outmux, compute);
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//Multipy variable-alpha^5
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assign outmult[0] = outreg[0] ^ outreg[3];
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assign outmult[1] = outreg[1] ^ outreg[4];
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assign outmult[2] = outreg[0] ^ outreg[2] ^ outreg[3];
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assign outmult[3] = outreg[1] ^ outreg[3] ^ outreg[4];
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assign outmult[4] = outreg[2] ^ outreg[4];
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assign out = outreg;
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endmodule
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//********************************************************//
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// Module that computes term with degree six. //
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// Constructed by a variable-constant multiplier with //
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// alpha^6 as constant. //
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//********************************************************//
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module degree6_cell(in, out, clock, load, compute);
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input [4:0] in;
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output [4:0] out;
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input clock, load, compute;
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wire [4:0] outmux;
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wire [0:4] outmult, outreg;
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register5_wl register(outmux, outreg, clock, load);
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mux2_to_1 multiplexer(in, outmult, outmux, compute);
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//Multipy variable-alpha^6
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assign outmult[0] = outreg[2] ^ outreg[4];
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assign outmult[1] = outreg[0] ^ outreg[3];
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assign outmult[2] = outreg[1] ^ outreg[2];
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assign outmult[3] = outreg[0] ^ outreg[2] ^ outreg[3];
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assign outmult[4] = outreg[1] ^ outreg[3] ^ outreg[4];
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assign out = outreg;
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endmodule
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//***********************************************************//
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// Invers Multiplication module for GF(2^5) is formed by AND //
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// and XOR gates. This module is derived directly from //
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// Fermat Theorem, which state that //
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// beta^(-1) = beta^2.beta^(2^2).beta^(2^3).beta^(2^4), //
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// for beta member of GF(2^5). //
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// Note: this module is only used in CSEE block //
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//***********************************************************//
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module inverscomb(in, out);
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input [0:4] in;
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output [0:4] out;
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//form product consists of AND gates
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wire p0, p1, p2, p3, p4 , p5 , p6, p7, p8, p9,
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p10, p11, p12, p13, p14, p15, p16, p17, p18,
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p19, p20, p21, p22, p23, p24;
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//form intermediate sum of the product that can be reused
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wire s0, s1, s2, s3, s4, s5, s6;
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//form intermediate sum of product that is only used by single function
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wire t0, t1, t2;
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assign p0 = in[0]&in[1];
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assign p1 = in[0]&in[2];
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assign p2 = in[0]&in[3];
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assign p3 = in[0]&in[4];
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assign p4 = in[1]&in[2];
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assign p5 = in[1]&in[3];
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assign p6 = in[1]&in[4];
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assign p7 = in[2]&in[4];
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assign p8 = in[3]&in[4];
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assign p9 = in[2]&in[3];
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assign p10 = p0&in[2];
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assign p11 = p0&in[4];
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assign p12 = p2&in[4];
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assign p13 = p9&in[0];
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assign p14 = p4&in[3];
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assign p15 = p8&in[2];
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assign p16 = p7&in[1];
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assign p17 = p2&in[1];
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assign p18 = p3&in[2];
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assign p19 = p6&in[3];
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assign p20 = p4&p8;
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assign p21 = p1&p5;
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assign p22 = p3&p5;
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assign p23 = p2&p7;
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assign p24 = p1&p6;
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assign s0 = p1 ^ p15;
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assign s1 = ((p6 ^ p12) ^ p14);
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assign s2 = (in[4] ^ p0) ^ p21;
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assign s3 = (in[1] ^ in[3]) ^ (p2 ^ p3) ^ (p24 ^ p10);
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assign s4 = (p4 ^ p5) ^ (p20 ^ p7) ^ p17;
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assign s5 = (in[2] ^ p5) ^ (p22 ^ p23);
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assign s6 = p11 ^ p20;
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assign t0 = (in[0] ^ p2) ^ (p4 ^ p10);
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assign t1 = (in[3] ^ p0) ^ p24;
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assign t2 = p19 ^ p23;
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assign out[0] = ((s0 ^ s1) ^ (s2 ^ s5)) ^ ((s6 ^ p13) ^ t0);
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assign out[1] = ((s0 ^ s1) ^ s2) ^ (s3 ^ (s6 ^ p16));
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assign out[2] = (s0 ^ s4) ^ ((p13 ^ p8) ^ t1);
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assign out[3] = ((s0 ^ s1) ^ (s2 ^ s5)) ^ ((p16 ^ p8) ^ (p9 ^ p18) ^ p7);
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assign out[4] = (s0 ^ s1) ^ (s3 ^ s4) ^ (p9 ^ t2);
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endmodule
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