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//********************************************************//
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// FIFO Register stores 31 recieved word symbols //
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//********************************************************//
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module fifo_register(clock1, clock2, shift_fifo, hold_fifo,
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en_outfifo, en_infifo, datain, dataout);
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input clock1, clock2;
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input shift_fifo, hold_fifo, en_outfifo, en_infifo;
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input [4:0] datain;
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output [4:0] dataout;
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wire [4:0] outreg0, outreg1, outreg2, outreg3, outreg4,
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outreg5, outreg6, outreg7, outreg8, outreg9,
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outreg10, outreg11, outreg12, outreg13, outreg14,
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outreg15, outreg16, outreg17, outreg18, outreg19,
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outreg20, outreg21, outreg22, outreg23, outreg24,
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outreg25, outreg26, outreg27, outreg28, outreg29,
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outreg30;
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wire [4:0] inputzero;
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reg [4:0] outmux;
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assign inputzero = 5'b0;
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always@(en_infifo or inputzero or datain)
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begin
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case(en_infifo)
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0 : outmux = inputzero;
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1 : outmux = datain;
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endcase
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end
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// 31 registers storing received words operate on clock1 //
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register5_wlh Reg0(outmux, outreg0, shift_fifo, hold_fifo, clock1);
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register5_wlh Reg1(outreg0, outreg1, shift_fifo, hold_fifo, clock1);
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register5_wlh Reg2(outreg1, outreg2, shift_fifo, hold_fifo, clock1);
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register5_wlh Reg3(outreg2, outreg3, shift_fifo, hold_fifo, clock1);
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register5_wlh Reg4(outreg3, outreg4, shift_fifo, hold_fifo, clock1);
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register5_wlh Reg5(outreg4, outreg5, shift_fifo, hold_fifo, clock1);
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register5_wlh Reg6(outreg5, outreg6, shift_fifo, hold_fifo, clock1);
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register5_wlh Reg7(outreg6, outreg7, shift_fifo, hold_fifo, clock1);
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register5_wlh Reg8(outreg7, outreg8, shift_fifo, hold_fifo, clock1);
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register5_wlh Reg9(outreg8, outreg9, shift_fifo, hold_fifo, clock1);
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register5_wlh Reg10(outreg9, outreg10, shift_fifo, hold_fifo, clock1);
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register5_wlh Reg11(outreg10, outreg11, shift_fifo, hold_fifo, clock1);
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register5_wlh Reg12(outreg11, outreg12, shift_fifo, hold_fifo, clock1);
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register5_wlh Reg13(outreg12, outreg13, shift_fifo, hold_fifo, clock1);
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register5_wlh Reg14(outreg13, outreg14, shift_fifo, hold_fifo, clock1);
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register5_wlh Reg15(outreg14, outreg15, shift_fifo, hold_fifo, clock1);
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register5_wlh Reg16(outreg15, outreg16, shift_fifo, hold_fifo, clock1);
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register5_wlh Reg17(outreg16, outreg17, shift_fifo, hold_fifo, clock1);
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register5_wlh Reg18(outreg17, outreg18, shift_fifo, hold_fifo, clock1);
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register5_wlh Reg19(outreg18, outreg19, shift_fifo, hold_fifo, clock1);
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register5_wlh Reg20(outreg19, outreg20, shift_fifo, hold_fifo, clock1);
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register5_wlh Reg21(outreg20, outreg21, shift_fifo, hold_fifo, clock1);
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register5_wlh Reg22(outreg21, outreg22, shift_fifo, hold_fifo, clock1);
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register5_wlh Reg23(outreg22, outreg23, shift_fifo, hold_fifo, clock1);
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register5_wlh Reg24(outreg23, outreg24, shift_fifo, hold_fifo, clock1);
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register5_wlh Reg25(outreg24, outreg25, shift_fifo, hold_fifo, clock1);
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register5_wlh Reg26(outreg25, outreg26, shift_fifo, hold_fifo, clock1);
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register5_wlh Reg27(outreg26, outreg27, shift_fifo, hold_fifo, clock1);
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register5_wlh Reg28(outreg27, outreg28, shift_fifo, hold_fifo, clock1);
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register5_wlh Reg29(outreg28, outreg29, shift_fifo, hold_fifo, clock1);
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register5_wlh Reg30(outreg29, outreg30, shift_fifo, hold_fifo, clock1);
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// Output register operates on clock2 to synchronize with //
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// output of CSEE. //
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register5_wl outreg(outreg30, dataout, clock2, en_outfifo);
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endmodule
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