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[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [CALLF.v] - Diff between revs 2 and 7

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//=============================================================================
//=============================================================================
//  CALL FAR and CALL FAR indirect
//  CALL FAR and CALL FAR indirect
//
//
//
//
//  2009-2012 Robert Finch
//  2009-2013 Robert Finch
//  Stratford
//  Stratford
//  robfinch<remove>@opencores.org
//  robfinch<remove>@finitron.ca
//
//
//
//
// This source file is free software: you can redistribute it and/or modify 
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// by the Free Software Foundation, either version 3 of the License, or     
Line 23... Line 23...
//
//
//=============================================================================
//=============================================================================
//
//
CALLF:
CALLF:
        begin
        begin
                `INITIATE_STACK_WRITE
                write(`CT_WRMEM,sssp,cs[15:8]);
                lock_o <= 1'b1;
                lock_o <= 1'b1;
                dat_o <= cs[15:8];
 
                state <= CALLF1;
                state <= CALLF1;
        end
        end
CALLF1:
CALLF1:
        if (ack_i) begin
        if (ack_i) begin
                `PAUSE_STACK_WRITE
                pause_stack_push();
                state <= CALLF2;
                state <= CALLF2;
        end
        end
CALLF2:
CALLF2:
        begin
        begin
                `INITIATE_STACK_WRITE
                write(`CT_WRMEM,sssp,cs[7:0]);
                dat_o <= cs[7:0];
 
                state <= CALLF3;
                state <= CALLF3;
        end
        end
CALLF3:
CALLF3:
        if (ack_i) begin
        if (ack_i) begin
                `PAUSE_STACK_WRITE
                pause_stack_push();
                state <= CALLF4;
                state <= CALLF4;
        end
        end
CALLF4:
CALLF4:
        begin
        begin
                `INITIATE_STACK_WRITE
                write(`CT_WRMEM,sssp,ip[15:8]);
                dat_o <= ip[15:8];
 
                state <= CALLF5;
                state <= CALLF5;
        end
        end
CALLF5:
CALLF5:
        if (ack_i) begin
        if (ack_i) begin
                `PAUSE_STACK_WRITE
                pause_stack_push();
                state <= CALLF6;
                state <= CALLF6;
        end
        end
CALLF6:
CALLF6:
        begin
        begin
                `INITIATE_STACK_WRITE
                write(`CT_WRMEM,sssp,ip[7:0]);
                dat_o <= ip[7:0];
 
                state <= CALLF7;
                state <= CALLF7;
        end
        end
CALLF7:
CALLF7:
        if (ack_i) begin
        if (ack_i) begin
                `TERMINATE_CYCLE
                nack();
                if (ir==8'hFF && rrr==3'b011)   // CALL FAR indirect
                if (ir==8'hFF && rrr==3'b011)   // CALL FAR indirect
                        state <= JUMP_VECTOR1;
                        state <= JUMP_VECTOR1;
                else begin
                else begin
                        cs <= selector;
                        cs <= selector;
                        ip <= offset;
                        ip <= offset;

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