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// ============================================================================
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// ============================================================================
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// CONTROL_LOGIC
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// CONTROL_LOGIC
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// - assorted control logic
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// - assorted control logic
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//
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//
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//
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//
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// (C) 2009,2010 Robert Finch
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// (C) 2009,2010,2013 Robert Finch
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// robfinch[remove]@opencores.org
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// robfinch[remove]@finitron.ca
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//
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//
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// by the Free Software Foundation, either version 3 of the License, or
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wire hasPrefix = prefix1!=8'h00;
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wire hasPrefix = prefix1!=8'h00;
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wire hasDoublePrefix = hasPrefix && prefix2!=8'h00;
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wire hasDoublePrefix = hasPrefix && prefix2!=8'h00;
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wire repz = prefix1==`REPZ || prefix2==`REPZ;
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wire repz = prefix1==`REPZ || prefix2==`REPZ;
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wire repnz = prefix1==`REPNZ || prefix2==`REPNZ;
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wire repnz = prefix1==`REPNZ || prefix2==`REPNZ;
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// ZF is tested only for SCAS, CMPS
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wire repdone =
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wire repdone =
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((repz | repnz) & cxz) ||
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((repz | repnz) & cxz) ||
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(repz & !zf) ||
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(repz && !zf && (ir==`SCASB||ir==`SCASW||ir==`CMPSB||ir==`CMPSW)) ||
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(repnz & zf)
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(repnz && zf && (ir==`SCASB||ir==`SCASW||ir==`CMPSB||ir==`CMPSW))
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;
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;
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No newline at end of file
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No newline at end of file
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