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[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [EACALC.v] - Diff between revs 6 and 7

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Rev 6 Rev 7
Line 1... Line 1...
// ============================================================================
// ============================================================================
//  EACALC
//  EACALC
//  - calculation of effective address
//  - calculation of effective address
//
//
//
//
//  (C) 2009-2012  Robert Finch, Stratford
//  (C) 2009-2013  Robert Finch, Stratford
//  robfinch[remove]@opencores.org
//  robfinch[remove]@finitron.ca
//
//
//
//
// This source file is free software: you can redistribute it and/or modify 
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// by the Free Software Foundation, either version 3 of the License, or     
Line 267... Line 267...
                `XCHG_MEM:
                `XCHG_MEM:
                        begin
                        begin
//                              bus_locked <= 1'b1;
//                              bus_locked <= 1'b1;
                                state <= FETCH_DATA;
                                state <= FETCH_DATA;
                        end
                        end
 
                8'b1000100x:    // Move to memory
 
                        begin
 
                                $display("EACALC1: state <= STORE_DATA");
 
                                if (w && (offsdisp==16'hFFFF)) begin
 
                                        int_num <= 8'h0d;
 
                                        state <= INT;
 
                                end
 
                                else begin
 
                                        res <= rrro;
 
                                        state <= STORE_DATA;
 
                                end
 
                        end
                default:
                default:
                        begin
                        begin
 
                                $display("EACALC1: state <= FETCH_DATA");
                                if (w && (offsdisp==16'hFFFF)) begin
                                if (w && (offsdisp==16'hFFFF)) begin
                                        int_num <= 8'h0d;
                                        int_num <= 8'h0d;
                                        state <= INT;
                                        state <= INT;
                                end
                                end
                                else
                                else

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