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Subversion Repositories rtf8088

[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [EACALC.v] - Diff between revs 7 and 8

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Rev 7	Rev 8
Line 33...	Line 33...
`//`	`//`
`EACALC:`	`EACALC:`
`// Terminate an outstanding MODRM fetch cycle`	`// Terminate an outstanding MODRM fetch cycle`
`if (cyc_o) begin`	`if (cyc_o) begin`
`if (ack_i) begin`	`if (ack_i) begin`
`TERMINATE_CODE_READ	`term_code_read();`
`mod <= dat_i[7:6];`	`mod <= dat_i[7:6];`
`rrr <= dat_i[5:3];`	`rrr <= dat_i[5:3];`
`sreg3 <= dat_i[5:3];`	`sreg3 <= dat_i[5:3];`
`TTT <= dat_i[5:3];`	`TTT <= dat_i[5:3];`
`rm <= dat_i[2:0];`	`rm <= dat_i[2:0];`
Line 137...	Line 137...
`// shifts and rotates`	`// shifts and rotates`
`8'hD0,8'hD1,8'hD2,8'hD3:`	`8'hD0,8'hD1,8'hD2,8'hD3:`
`begin`	`begin`
`b <= rmo;`	`b <= rmo;`
`end`	`end`
	`// The TEST instruction is the only one needing to fetch an immediate value.`
`8'hF6,8'hF7:`	`8'hF6,8'hF7:`
	`// 000 = TEST`
	`// 010 = NOT`
	`// 011 = NEG`
	`// 100 = MUL`
	`// 101 = IMUL`
	`// 110 = DIV`
	`// 111 = IDIV`
	`if (rrr==3'b000) begin // TEST`
	`a <= rmo;`
	`state <= w ? FETCH_IMM16 : FETCH_IMM8;`
	`end`
	`else`
`b <= rmo;`	`b <= rmo;`
`default:`	`default:`
`begin`	`begin`
`if (d) begin`	`if (d) begin`
`a <= rmo;`	`a <= rmo;`
Line 163...	Line 176...
`//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -`	`//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -`
`//`	`//`
`EACALC_DISP16:`	`EACALC_DISP16:`
`begin`	`begin`
`lock_o <= 1'b1;`	`lock_o <= 1'b1;`
`INITIATE_CODE_READ	`code_read();`
`state <= EACALC_DISP16_ACK;`	`state <= EACALC_DISP16_ACK;`
`end`	`end`
`EACALC_DISP16_ACK:`	`EACALC_DISP16_ACK:`
`if (ack_i) begin`	`if (ack_i) begin`
`TERMINATE_CODE_READ	`term_code_read();`
`disp16[7:0] <= dat_i;`	`disp16[7:0] <= dat_i;`
`state <= EACALC_DISP16a;`	`state <= EACALC_DISP16a;`
`end`	`end`
`EACALC_DISP16a:`	`EACALC_DISP16a:`
`begin`	`begin`
`INITIATE_CODE_READ	`code_read();`
`state <= EACALC_DISP16a_ACK;`	`state <= EACALC_DISP16a_ACK;`
`end`	`end`
`EACALC_DISP16a_ACK:`	`EACALC_DISP16a_ACK:`
`if (ack_i) begin`	`if (ack_i) begin`
`TERMINATE_CODE_READ	`term_code_read();`
`lock_o <= bus_locked;`	`lock_o <= bus_locked;`
`disp16[15:8] <= dat_i;`	`disp16[15:8] <= dat_i;`
`state <= EACALC1;`	`state <= EACALC1;`
`end`	`end`

Line 191...	Line 204...
`// Fetch 8 bit displacement`	`// Fetch 8 bit displacement`
`//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -`	`//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -`
`//`	`//`
`EACALC_DISP8:`	`EACALC_DISP8:`
`begin`	`begin`
`INITIATE_CODE_READ	`code_read();`
`state <= EACALC_DISP8_ACK;`	`state <= EACALC_DISP8_ACK;`
`end`	`end`
`EACALC_DISP8_ACK:`	`EACALC_DISP8_ACK:`
`if (ack_i) begin`	`if (ack_i) begin`
`TERMINATE_CODE_READ	`term_code_read();`
`disp16 <= {{8{dat_i[7]}},dat_i};`	`disp16 <= {{8{dat_i[7]}},dat_i};`
`state <= EACALC1;`	`state <= EACALC1;`
`end`	`end`


Line 220...	Line 233...
`3'b011: state <= FETCH_DATA; // LTR`	`3'b011: state <= FETCH_DATA; // LTR`
`default: state <= FETCH_DATA;`	`default: state <= FETCH_DATA;`
`endcase`	`endcase`
`if (w && (offsdisp==16'hFFFF)) begin`	`if (w && (offsdisp==16'hFFFF)) begin`
`int_num <= 8'h0d;`	`int_num <= 8'h0d;`
`state <= INT;`	`state <= INT2;`
`end`	`end`
`end`	`end`
`8'h01:`	`8'h01:`
`begin`	`begin`
`case(rrr)`	`case(rrr)`
Line 232...	Line 245...
`3'b011: state <= FETCH_DESC;`	`3'b011: state <= FETCH_DESC;`
`default: state <= FETCH_DATA;`	`default: state <= FETCH_DATA;`
`endcase`	`endcase`
`if (w && (offsdisp==16'hFFFF)) begin`	`if (w && (offsdisp==16'hFFFF)) begin`
`int_num <= 8'h0d;`	`int_num <= 8'h0d;`
`state <= INT;`	`state <= INT2;`
`end`	`end`
`end`	`end`
`8'h03:`	`8'h03:`
`if (w && (offsdisp==16'hFFFF)) begin`	`if (w && (offsdisp==16'hFFFF)) begin`
`int_num <= 8'h0d;`	`int_num <= 8'h0d;`
`state <= INT;`	`state <= INT2;`
`end`	`end`
`else`	`else`
`state <= FETCH_DATA;`	`state <= FETCH_DATA;`
`default:`	`default:`
`if (w && (offsdisp==16'hFFFF)) begin`	`if (w && (offsdisp==16'hFFFF)) begin`
`int_num <= 8'h0d;`	`int_num <= 8'h0d;`
`state <= INT;`	`state <= INT2;`
`end`	`end`
`else`	`else`
`state <= FETCH_DATA;`	`state <= FETCH_DATA;`
`endcase`	`endcase`
`MOV_I8M: state <= FETCH_IMM8;	`MOV_I8M: state <= FETCH_IMM8;
`MOV_I16M:	`MOV_I16M:
`if (ip==16'hFFFF) begin`	`if (ip==16'hFFFF) begin`
`int_num <= 8'h0d;`	`int_num <= 8'h0d;`
`state <= INT;`	`state <= INT2;`
`end`	`end`
`else`	`else`
`state <= FETCH_IMM16;`	`state <= FETCH_IMM16;`
`POP_MEM:	`POP_MEM:
`begin`	`begin`
Line 272...	Line 285...
`8'b1000100x: // Move to memory`	`8'b1000100x: // Move to memory`
`begin`	`begin`
`$display("EACALC1: state <= STORE_DATA");`	`$display("EACALC1: state <= STORE_DATA");`
`if (w && (offsdisp==16'hFFFF)) begin`	`if (w && (offsdisp==16'hFFFF)) begin`
`int_num <= 8'h0d;`	`int_num <= 8'h0d;`
`state <= INT;`	`state <= INT2;`
`end`	`end`
`else begin`	`else begin`
`res <= rrro;`	`res <= rrro;`
`state <= STORE_DATA;`	`state <= STORE_DATA;`
`end`	`end`
Line 284...	Line 297...
`default:`	`default:`
`begin`	`begin`
`$display("EACALC1: state <= FETCH_DATA");`	`$display("EACALC1: state <= FETCH_DATA");`
`if (w && (offsdisp==16'hFFFF)) begin`	`if (w && (offsdisp==16'hFFFF)) begin`
`int_num <= 8'h0d;`	`int_num <= 8'h0d;`
`state <= INT;`	`state <= INT2;`
`end`	`end`
`else`	`else`
`state <= FETCH_DATA;`	`state <= FETCH_DATA;`
`if (ir==8'hff) begin`	`if (ir==8'hff) begin`
`case(rrr)`	`case(rrr)`

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[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [EACALC.v] - Diff between revs 7 and 8