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Subversion Repositories rtf8088

[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [EXECUTE.v] - Diff between revs 7 and 8

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Rev 7 Rev 8
Line 187... Line 187...
                                af <= carry   (1'b1,a[3],b[3],alu_o[3]);
                                af <= carry   (1'b1,a[3],b[3],alu_o[3]);
                                vf <= overflow(1'b1,a[15],b[15],resnw);
                                vf <= overflow(1'b1,a[15],b[15],resnw);
                                sf <= resnw;
                                sf <= resnw;
                                zf <= reszw;
                                zf <= reszw;
                        end
                        end
                `IMUL:
//              `IMUL:
                        begin
//                      begin
                                state <= IFETCH;
//                              state <= IFETCH;
                                wrregs <= 1'b1;
//                              wrregs <= 1'b1;
                                w <= 1'b1;
//                              w <= 1'b1;
                                rrr <= 3'd0;
//                              rrr <= 3'd0;
                                res <= alu_o;
//                              res <= alu_o;
                                if (w) begin
//                              if (w) begin
                                        cf <= wp[31:16]!={16{resnw}};
//                                      cf <= wp[31:16]!={16{resnw}};
                                        vf <= wp[31:16]!={16{resnw}};
//                                      vf <= wp[31:16]!={16{resnw}};
                                        dx <= wp[31:16];
//                                      dx <= wp[31:16];
                                end
//                              end
                                else begin
//                              else begin
                                        cf <= ah!={8{resnb}};
//                                      cf <= ah!={8{resnb}};
                                        vf <= ah!={8{resnb}};
//                                      vf <= ah!={8{resnb}};
                                end
//                              end
                        end
//                      end
 
 
 
 
                //-----------------------------------------------------------------
                //-----------------------------------------------------------------
                // Memory Operations
                // Memory Operations
                //-----------------------------------------------------------------
                //-----------------------------------------------------------------

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