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[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [IFETCH.v] - Diff between revs 4 and 7

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Rev 4	Rev 7
Line 34...	Line 34...
`//`	`//`
`//=============================================================================`	`//=============================================================================`
`//`	`//`
`IFETCH:`	`IFETCH:`
`begin`	`begin`
	`$display("CSIP: %h", csip);`
`// Reset all instruction processing flags at instruction fetch`	`// Reset all instruction processing flags at instruction fetch`
cyc_type <= `CT_PASSIVE;	cyc_type <= `CT_PASSIVE;
`mod <= 2'd0;`	`mod <= 2'd0;`
`rrr <= 3'd0;`	`rrr <= 3'd0;`
`rm <= 3'd0;`	`rm <= 3'd0;`
Line 75...	Line 76...
`state <= IFETCH;`	`state <= IFETCH;`
cyc_type <= `CT_HALT;	cyc_type <= `CT_HALT;
`end`	`end`
`else begin`	`else begin`
`state <= IFETCH_ACK;`	`state <= IFETCH_ACK;`
`INITIATE_CODE_READ	read(`CT_CODE,csip);
`inta_o <= 1'b0;`	`inta_o <= 1'b0;`
`mio_o <= 1'b1;`	`mio_o <= 1'b1;`
`lock_o <= bus_locked;`	`lock_o <= bus_locked;`
`end`	`end`
`end`	`end`

`IFETCH_ACK:`	`IFETCH_ACK:`
`if (ack_i) begin`	`if (ack_i) begin`
`TERMINATE_CODE_READ	`nack_ir();`
`ir <= dat_i;`
`$display("IR: %h",dat_i);`	`$display("IR: %h",dat_i);`
`if (!hasPrefix)`	`if (!hasPrefix)`
`ir_ip <= ip;`	`ir_ip <= ip;`
`// ir_ip <= dat_i;`	`// ir_ip <= dat_i;`
`w <= dat_i[0];`	`w <= dat_i[0];`
Line 104...	Line 104...

`// Fetch extended opcode`	`// Fetch extended opcode`
`//`	`//`
`XI_FETCH:`	`XI_FETCH:`
`begin`	`begin`
`INITIATE_CODE_READ	read(`CT_CODE,csip);
`state <= XI_FETCH_ACK;`	`state <= XI_FETCH_ACK;`
`end`	`end`

`XI_FETCH_ACK:`	`XI_FETCH_ACK:`
`if (ack_i) begin`	`if (ack_i) begin`
`TERMINATE_CODE_READ	`nack_ir2();`
`ir2 <= dat_i;`
`state <= DECODER2;`	`state <= DECODER2;`
`end`	`end`

`No newline at end of file`	`No newline at end of file`

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[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [IFETCH.v] - Diff between revs 4 and 7