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[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [STOS.v] - Diff between revs 2 and 8

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Rev 2 Rev 8
Line 1... Line 1...
//=============================================================================
//=============================================================================
//  STOSB,STOSW
//  STOSB,STOSW
//  Store string data to memory.
//  Store string data to memory.
//
//
//
//
//  2009-2012 Robert Finch
//  2009-2013 Robert Finch
//  Stratford
//  Stratford
//  robfinch<remove>@opencores.org
//  robfinch<remove>@finitron.ca
//
//
//
//
// This source file is free software: you can redistribute it and/or modify 
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// by the Free Software Foundation, either version 3 of the License, or     
Line 22... Line 22...
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//
//
//=============================================================================
//=============================================================================
//
//
STOS:
STOS:
`include "check_for_ints.v"
        if (pe_nmi) begin
 
                rst_nmi <= 1'b1;
 
                int_num <= 8'h02;
 
                ir <= `NOP;
 
                state <= INT2;
 
        end
 
        else if (irq_i & ie) begin
 
                ir <= `NOP;
 
                state <= INTA0;
 
        end
        else if (w && (di==16'hFFFF)) begin
        else if (w && (di==16'hFFFF)) begin
                ir <= `NOP;
                ir <= `NOP;
                int_num <= 8'd13;
                int_num <= 8'd13;
                state <= INT1;
                state <= INT2;
        end
        end
        else if (repdone)
        else if (repdone)
                state <= IFETCH;
                state <= IFETCH;
        else begin
        else begin
                if (!cyc_o) begin
                if (!cyc_o) begin

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