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https://opencores.org/ocsvn/sdram_controller/sdram_controller/trunk
[/] [sdram_controller/] [trunk/] [sdram.vhd] - Diff between revs 18 and 19
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| Rev 18 |
Rev 19 |
| Line 456... |
Line 456... |
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debug_reg <= x"00";
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debug_reg <= x"00";
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dram_cs <= '0';
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dram_cs <= '0';
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data_o <= data1_o when addr_save(0) = '1' else data0_o;
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data_o <= data1_o when addr_save(0) = '1' else data0_o;
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-- process (clk_000)
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-- begin
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-- if (cap_en = '1') then
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-- if (rising_edge(clk_000)) then
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-- addr_save <= addr;
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-- datai_save <= data_i;
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-- op_save <= op;
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-- end if;
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-- end if;
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-- end process;
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-- this will probably make the synthesizer scream bloody murder
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-- over either a transparent latch or gated clock or both
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-- but i've got it working again with my SoC and I'll see about
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-- changing it back to something less icky later
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--
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-- capture addr, data_i and op for the cmd fsm
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-- capture addr, data_i and op for the cmd fsm
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-- op needs to be captured during AR or it might get dropped
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-- op needs to be captured during AR or it might get dropped
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addr_save <= addr when cap_en = '1' else addr_save;
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process (clk_000)
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datai_save <= data_i when cap_en = '1' else datai_save;
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begin
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op_save <= op when cap_en = '1' else op_save;
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if (cap_en = '1') then
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if (rising_edge(clk_000)) then
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addr_save <= addr;
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datai_save <= data_i;
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op_save <= op;
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end if;
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end if;
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end process;
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-- command state machine
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-- command state machine
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process (clk_000)
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process (clk_000)
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begin
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begin
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if (rising_edge(clk_000)) then
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if (rising_edge(clk_000)) then
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