URL
https://opencores.org/ocsvn/sdram_controller/sdram_controller/trunk
[/] [sdram_controller/] [trunk/] [sdram_reader.vhd] - Diff between revs 6 and 7
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Rev 7 |
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Line 27... |
---- Uncomment the following library declaration if instantiating
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--library UNISIM;
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--use UNISIM.VComponents.all;
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--use UNISIM.VComponents.all;
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-- I strongly suggest you run this in the post-PAR simulator first and then start making changes to it
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-- I strongly suggest you run this in the post-PAR simulator first and then start
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-- after looking at what goes on at the post-PAR level. Don't say I didn't warn you.
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-- making changes to it after looking at what goes on at the post-PAR level. Don't
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-- Why didn't I use the IDDR2 primitives? Map'nPack keeps bitching about how it won't fit into the IOBs
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-- say I didn't warn you.
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-- with the ODDR2 primitives. I decided the ODDR2s were more important to keep.
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-- Why didn't I use the IDDR2 primitives? Map'nPack keeps bitching about how it
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-- I'm just capturing the front side of the burst, and letting the back side of the burst fall on the
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-- won't fit into the IOBs with the ODDR2 primitives. I decided the ODDR2s were
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-- floor. If you want to support both sides of the 2 burst or bigger bursts, you'll need to rework this.
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-- more important to keep.
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-- I'm just capturing the front side of the burst, and letting the back side of
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-- the burst fall on the floor. If you want to support both sides of the 2 burst
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-- or bigger bursts, you'll need to rework this.
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entity sdram_reader is
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entity sdram_reader is
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port(
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port(
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clk270 : in std_logic;
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clk270 : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
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dq : in std_logic_vector(15 downto 0);
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dq : in std_logic_vector(15 downto 0);
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