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Line 85... |
//
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//
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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`default_nettype none
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//
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`define LLSDSPI_IDLE 4'h0
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`define LLSDSPI_IDLE 4'h0
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`define LLSDSPI_HOTIDLE 4'h1
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`define LLSDSPI_HOTIDLE 4'h1
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`define LLSDSPI_WAIT 4'h2
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`define LLSDSPI_WAIT 4'h2
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`define LLSDSPI_START 4'h3
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`define LLSDSPI_START 4'h3
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//
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//
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module llsdspi(i_clk, i_speed, i_cs, i_stb, i_byte,
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module llsdspi(i_clk, i_speed, i_cs, i_stb, i_byte,
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o_cs_n, o_sclk, o_mosi, i_miso,
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o_cs_n, o_sclk, o_mosi, i_miso,
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o_stb, o_byte, o_idle, i_bus_grant);
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o_stb, o_byte, o_idle, i_bus_grant);
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parameter SPDBITS = 7;
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parameter SPDBITS = 7;
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//
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//
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input i_clk;
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input wire i_clk;
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// Parameters/setup
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// Parameters/setup
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input [(SPDBITS-1):0] i_speed;
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input wire [(SPDBITS-1):0] i_speed;
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// The incoming interface
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// The incoming interface
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input i_cs;
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input wire i_cs;
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input i_stb;
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input wire i_stb;
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input [7:0] i_byte;
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input wire [7:0] i_byte;
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// The actual SPI interface
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// The actual SPI interface
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output reg o_cs_n, o_sclk, o_mosi;
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output reg o_cs_n, o_sclk, o_mosi;
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input i_miso;
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input wire i_miso;
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// The outgoing interface
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// The outgoing interface
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output reg o_stb;
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output reg o_stb;
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output reg [7:0] o_byte;
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output reg [7:0] o_byte;
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output wire o_idle;
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output wire o_idle;
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// And whether or not we actually own the interface (yet)
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// And whether or not we actually own the interface (yet)
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input i_bus_grant;
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input wire i_bus_grant;
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reg r_z_counter;
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reg r_z_counter;
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reg [(SPDBITS-1):0] r_clk_counter;
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reg [(SPDBITS-1):0] r_clk_counter;
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reg r_idle;
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reg r_idle;
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reg [3:0] r_state;
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reg [3:0] r_state;
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assign byte_accepted = (i_stb)&&(o_idle);
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assign byte_accepted = (i_stb)&&(o_idle);
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initial r_clk_counter = 7'h0;
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initial r_clk_counter = 7'h0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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if ((~i_cs)||(~i_bus_grant))
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if ((!i_cs)||(!i_bus_grant))
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r_clk_counter <= 0;
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r_clk_counter <= 0;
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else if (byte_accepted)
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else if (byte_accepted)
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r_clk_counter <= i_speed;
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r_clk_counter <= i_speed;
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else if (~r_z_counter)
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else if (!r_z_counter)
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r_clk_counter <= (r_clk_counter - {{(SPDBITS-1){1'b0}},1'b1});
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r_clk_counter <= (r_clk_counter - {{(SPDBITS-1){1'b0}},1'b1});
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else if ((r_state != `LLSDSPI_IDLE)&&(r_state != `LLSDSPI_HOTIDLE))
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else if ((r_state != `LLSDSPI_IDLE)&&(r_state != `LLSDSPI_HOTIDLE))
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r_clk_counter <= (i_speed);
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r_clk_counter <= (i_speed);
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// else
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// else
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// r_clk_counter <= 16'h00;
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// r_clk_counter <= 16'h00;
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end
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end
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initial r_z_counter = 1'b1;
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initial r_z_counter = 1'b1;
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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if ((~i_cs)||(~i_bus_grant))
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if ((!i_cs)||(!i_bus_grant))
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r_z_counter <= 1'b1;
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r_z_counter <= 1'b1;
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else if (byte_accepted)
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else if (byte_accepted)
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r_z_counter <= 1'b0;
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r_z_counter <= 1'b0;
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else if (~r_z_counter)
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else if (!r_z_counter)
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r_z_counter <= (r_clk_counter == 1);
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r_z_counter <= (r_clk_counter == 1);
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else if ((r_state != `LLSDSPI_IDLE)&&(r_state != `LLSDSPI_HOTIDLE))
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else if ((r_state != `LLSDSPI_IDLE)&&(r_state != `LLSDSPI_HOTIDLE))
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r_z_counter <= 1'b0;
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r_z_counter <= 1'b0;
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end
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end
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initial r_state = `LLSDSPI_IDLE;
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initial r_state = `LLSDSPI_IDLE;
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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o_stb <= 1'b0;
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o_stb <= 1'b0;
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o_cs_n <= ~i_cs;
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o_cs_n <= !i_cs;
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if (~i_cs)
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if (!i_cs)
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begin
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begin
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r_state <= `LLSDSPI_IDLE;
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r_state <= `LLSDSPI_IDLE;
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r_idle <= 1'b0;
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r_idle <= 1'b0;
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o_sclk <= 1'b1;
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o_sclk <= 1'b1;
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end else if (~r_z_counter)
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end else if (!r_z_counter)
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begin
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begin
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r_idle <= 1'b0;
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r_idle <= 1'b0;
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if (byte_accepted)
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if (byte_accepted)
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begin // Will only happen within a hot idle state
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begin // Will only happen within a hot idle state
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r_byte <= { i_byte[6:0], 1'b1 };
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r_byte <= { i_byte[6:0], 1'b1 };
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