| Line 9... |
Line 9... |
// Creator: Dan Gisselquist, Ph.D.
|
// Creator: Dan Gisselquist, Ph.D.
|
// Gisselquist Technology, LLC
|
// Gisselquist Technology, LLC
|
//
|
//
|
////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////
|
//
|
//
|
// Copyright (C) 2016, Gisselquist Technology, LLC
|
// Copyright (C) 2016-2017, Gisselquist Technology, LLC
|
//
|
//
|
// This program is free software (firmware): you can redistribute it and/or
|
// This program is free software (firmware): you can redistribute it and/or
|
// modify it under the terms of the GNU General Public License as published
|
// modify it under the terms of the GNU General Public License as published
|
// by the Free Software Foundation, either version 3 of the License, or (at
|
// by the Free Software Foundation, either version 3 of the License, or (at
|
// your option) any later version.
|
// your option) any later version.
|
| Line 22... |
Line 22... |
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
|
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
|
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
// for more details.
|
// for more details.
|
//
|
//
|
// You should have received a copy of the GNU General Public License along
|
// You should have received a copy of the GNU General Public License along
|
// with this program. (It's in the $(ROOT)/doc directory, run make with no
|
// with this program. (It's in the $(ROOT)/doc directory. Run make with no
|
// target there if the PDF file isn't present.) If not, see
|
// target there if the PDF file isn't present.) If not, see
|
// <http://www.gnu.org/licenses/> for a copy.
|
// <http://www.gnu.org/licenses/> for a copy.
|
//
|
//
|
// License: GPL, v3, as defined and found on www.gnu.org,
|
// License: GPL, v3, as defined and found on www.gnu.org,
|
// http://www.gnu.org/licenses/gpl.html
|
// http://www.gnu.org/licenses/gpl.html
|
//
|
//
|
//
|
//
|
////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////
|
//
|
//
|
//
|
//
|
|
`default_nettype none
|
|
//
|
`define SDSPI_CMD_ADDRESS 2'h0
|
`define SDSPI_CMD_ADDRESS 2'h0
|
`define SDSPI_DAT_ADDRESS 2'h1
|
`define SDSPI_DAT_ADDRESS 2'h1
|
`define SDSPI_FIFO_A_ADDR 2'h2
|
`define SDSPI_FIFO_A_ADDR 2'h2
|
`define SDSPI_FIFO_B_ADDR 2'h3
|
`define SDSPI_FIFO_B_ADDR 2'h3
|
//
|
//
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| Line 72... |
Line 74... |
// And whether or not we own the bus
|
// And whether or not we own the bus
|
i_bus_grant,
|
i_bus_grant,
|
// And some wires for debugging it all
|
// And some wires for debugging it all
|
o_debug);
|
o_debug);
|
parameter LGFIFOLN = 7;
|
parameter LGFIFOLN = 7;
|
input i_clk;
|
input wire i_clk;
|
//
|
//
|
input i_wb_cyc, i_wb_stb, i_wb_we;
|
input wire i_wb_cyc, i_wb_stb, i_wb_we;
|
input [1:0] i_wb_addr;
|
input wire [1:0] i_wb_addr;
|
input [31:0] i_wb_data;
|
input wire [31:0] i_wb_data;
|
output reg o_wb_ack;
|
output reg o_wb_ack;
|
output wire o_wb_stall;
|
output wire o_wb_stall;
|
output reg [31:0] o_wb_data;
|
output reg [31:0] o_wb_data;
|
//
|
//
|
output wire o_cs_n, o_sck, o_mosi;
|
output wire o_cs_n, o_sck, o_mosi;
|
input i_miso;
|
input wire i_miso;
|
// The interrupt
|
// The interrupt
|
output reg o_int;
|
output reg o_int;
|
// .. and whether or not we can use the SPI port
|
// .. and whether or not we can use the SPI port
|
input i_bus_grant;
|
input wire i_bus_grant;
|
//
|
//
|
output wire [31:0] o_debug;
|
output wire [31:0] o_debug;
|
|
|
//
|
//
|
// Some WB simplifications:
|
// Some WB simplifications:
|
//
|
//
|
reg r_cmd_busy;
|
reg r_cmd_busy;
|
|
|
|
wire wb_stb, write_stb, cmd_stb, new_data, new_cmd;
|
|
wire [1:0] wb_addr;
|
|
wire [31:0] wb_data;
|
|
`ifdef WB_CLOCK
|
wire wb_stb, write_stb, cmd_stb; // read_stb
|
wire wb_stb, write_stb, cmd_stb; // read_stb
|
assign wb_stb = ((i_wb_cyc)&&(i_wb_stb)&&(~o_wb_stall));
|
assign wb_stb = ((i_wb_stb)&&(!o_wb_stall));
|
assign write_stb = ((wb_stb)&&( i_wb_we));
|
assign write_stb = ((wb_stb)&&( i_wb_we));
|
// assign read_stb = ((wb_stb)&&(~i_wb_we));
|
// assign read_stb = ((wb_stb)&&(!i_wb_we));
|
assign cmd_stb = (~r_cmd_busy)&&(write_stb)
|
assign cmd_stb = (!r_cmd_busy)&&(write_stb)
|
|
&&(i_wb_addr==`SDSPI_CMD_ADDRESS);
|
|
assign wb_addr = i_wb_addr;
|
|
assign wb_data = i_wb_data;
|
|
assign new_cmd = cmd_stb;
|
|
assign new_data = (i_wb_stb)&&(!o_wb_stall)&&(i_wb_we)
|
|
&&(i_wb_addr == `SDSPI_DAT_ADDRESS);
|
|
`else
|
|
reg r_wb_stb, r_write_stb, r_cmd_stb, r_new_data;
|
|
reg [1:0] r_wb_addr;
|
|
reg [31:0] r_wb_data;
|
|
always @(posedge i_clk)
|
|
r_wb_stb <= ((i_wb_stb)&&(!o_wb_stall));
|
|
always @(posedge i_clk)
|
|
r_write_stb <= ((i_wb_stb)&&(!o_wb_stall)&&(i_wb_we));
|
|
always @(posedge i_clk)
|
|
r_cmd_stb <= (!r_cmd_busy)&&(i_wb_stb)&&(!o_wb_stall)&&(i_wb_we)
|
&&(i_wb_addr==`SDSPI_CMD_ADDRESS);
|
&&(i_wb_addr==`SDSPI_CMD_ADDRESS);
|
|
always @(posedge i_clk)
|
|
r_new_data <= (i_wb_stb)&&(!o_wb_stall)&&(i_wb_we)
|
|
&&(i_wb_addr == `SDSPI_DAT_ADDRESS);
|
|
always @(posedge i_clk)
|
|
r_wb_addr <= i_wb_addr;
|
|
always @(posedge i_clk)
|
|
r_wb_data <= i_wb_data;
|
|
|
|
assign wb_stb = r_wb_stb;
|
|
assign write_stb= r_write_stb;
|
|
assign cmd_stb = r_cmd_stb;
|
|
assign new_cmd = r_cmd_stb;
|
|
assign new_data = r_new_data;
|
|
assign wb_addr = r_wb_addr;
|
|
assign wb_data = r_wb_data;
|
|
`endif
|
|
|
|
|
//
|
//
|
// Access to our lower-level SDSPI driver, the one that actually
|
// Access to our lower-level SDSPI driver, the one that actually
|
// uses/sets the SPI ports
|
// uses/sets the SPI ports
|
| Line 128... |
Line 167... |
reg r_have_resp, r_use_fifo, r_fifo_wr,
|
reg r_have_resp, r_use_fifo, r_fifo_wr,
|
ll_fifo_rd_complete, ll_fifo_wr_complete,
|
ll_fifo_rd_complete, ll_fifo_wr_complete,
|
r_fifo_id,
|
r_fifo_id,
|
ll_fifo_wr, ll_fifo_rd,
|
ll_fifo_wr, ll_fifo_rd,
|
r_have_data_response_token,
|
r_have_data_response_token,
|
r_have_start_token;
|
r_have_start_token,
|
|
r_err_token;
|
|
reg [3:0] r_read_err_token;
|
|
reg [1:0] r_data_response_token;
|
reg [7:0] fifo_byte;
|
reg [7:0] fifo_byte;
|
reg [7:0] r_last_r_one;
|
reg [7:0] r_last_r_one;
|
//
|
//
|
reg [31:0] r_data_reg;
|
reg [31:0] r_data_reg;
|
reg [1:0] r_data_fil, r_cmd_resp;
|
reg [1:0] r_data_fil, r_cmd_resp;
|
| Line 143... |
Line 185... |
reg r_cmd_sent;
|
reg r_cmd_sent;
|
reg [31:0] fifo_a_reg, fifo_b_reg;
|
reg [31:0] fifo_a_reg, fifo_b_reg;
|
//
|
//
|
reg q_busy;
|
reg q_busy;
|
//
|
//
|
reg [7:0] fifo_a_mem[((1<<(LGFIFOLN+2))-1):0];
|
reg [7:0] fifo_a_mem_0[0:((1<<LGFIFOLN)-1)],
|
reg [7:0] fifo_b_mem[((1<<(LGFIFOLN+2))-1):0];
|
fifo_a_mem_1[0:((1<<LGFIFOLN)-1)],
|
|
fifo_a_mem_2[0:((1<<LGFIFOLN)-1)],
|
|
fifo_a_mem_3[0:((1<<LGFIFOLN)-1)],
|
|
fifo_b_mem_0[0:((1<<LGFIFOLN)-1)],
|
|
fifo_b_mem_1[0:((1<<LGFIFOLN)-1)],
|
|
fifo_b_mem_2[0:((1<<LGFIFOLN)-1)],
|
|
fifo_b_mem_3[0:((1<<LGFIFOLN)-1)];
|
reg [(LGFIFOLN-1):0] fifo_wb_addr;
|
reg [(LGFIFOLN-1):0] fifo_wb_addr;
|
reg [(LGFIFOLN+1):0] rd_fifo_sd_addr;
|
|
reg [(LGFIFOLN+1):0] wr_fifo_sd_addr;
|
|
//
|
//
|
reg [(LGFIFOLN+1):0] ll_fifo_addr;
|
reg [(LGFIFOLN+1):0] ll_fifo_addr;
|
//
|
//
|
reg fifo_crc_err;
|
reg fifo_crc_err;
|
reg [1:0] ll_fifo_wr_state;
|
reg [1:0] ll_fifo_wr_state;
|
| Line 174... |
Line 220... |
//
|
//
|
reg [25:0] r_watchdog;
|
reg [25:0] r_watchdog;
|
reg r_watchdog_err;
|
reg r_watchdog_err;
|
reg pre_cmd_state;
|
reg pre_cmd_state;
|
|
|
|
// Relieve some stress from the WB bus timing
|
|
|
initial r_cmd_busy = 1'b0;
|
initial r_cmd_busy = 1'b0;
|
initial r_data_reg = 32'h00;
|
initial r_data_reg = 32'h00;
|
initial r_last_r_one = 8'hff;
|
initial r_last_r_one = 8'hff;
|
initial ll_cmd_stb = 1'b0;
|
initial ll_cmd_stb = 1'b0;
|
initial ll_fifo_rd = 1'b0;
|
initial ll_fifo_rd = 1'b0;
|
| Line 188... |
Line 236... |
initial r_data_fil = 2'b00;
|
initial r_data_fil = 2'b00;
|
initial r_lgblklen = LGFIFOLN;
|
initial r_lgblklen = LGFIFOLN;
|
initial r_cmd_err = 1'b0;
|
initial r_cmd_err = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
begin
|
begin
|
if (~ll_cmd_stb)
|
if (!ll_cmd_stb)
|
begin
|
begin
|
r_have_resp <= 1'b0;
|
r_have_resp <= 1'b0;
|
ll_fifo_wr <= 1'b0;
|
ll_fifo_wr <= 1'b0;
|
ll_fifo_rd <= 1'b0;
|
ll_fifo_rd <= 1'b0;
|
// r_rsp_state <= 3'h0;
|
// r_rsp_state <= 3'h0;
|
| Line 271... |
Line 319... |
// expecting from the SDCard, and r_rsp_state, the
|
// expecting from the SDCard, and r_rsp_state, the
|
// state machine for where we are at receive what we
|
// state machine for where we are at receive what we
|
// are expecting.
|
// are expecting.
|
if (pre_rsp_state)
|
if (pre_rsp_state)
|
begin
|
begin
|
if (r_rsp_state == `SDSPI_RSP_NONE)
|
case(r_rsp_state)
|
begin // Waiting on R1
|
`SDSPI_RSP_NONE: begin // Waiting on R1
|
if (~ll_out_dat[7])
|
if (!ll_out_dat[7])
|
begin
|
begin
|
r_last_r_one <= ll_out_dat;
|
r_last_r_one <= ll_out_dat;
|
if (r_cmd_resp == `SDSPI_EXPECT_R1)
|
if (r_cmd_resp == `SDSPI_EXPECT_R1)
|
begin // Expecting R1 alone
|
begin // Expecting R1 alone
|
r_have_resp <= 1'b1;
|
r_have_resp <= 1'b1;
|
ll_cmd_stb <= (r_use_fifo);
|
ll_cmd_stb <= (r_use_fifo);
|
r_data_reg <= 32'hffffffff;
|
r_data_reg <= 32'hffffffff;
|
ll_fifo_wr<=(r_use_fifo)&&(~r_fifo_wr);
|
ll_fifo_wr<=(r_use_fifo)&&(!r_fifo_wr);
|
end else if (r_cmd_resp == `SDSPI_EXPECT_R1B)
|
end else if (r_cmd_resp == `SDSPI_EXPECT_R1B)
|
begin // Go wait on R1b
|
begin // Go wait on R1b
|
r_data_reg <= 32'hffffffff;
|
r_data_reg <= 32'hffffffff;
|
end // else wait on 32-bit rsp
|
end // else wait on 32-bit rsp
|
end
|
end end
|
end else if (r_rsp_state == `SDSPI_RSP_BSYWAIT)
|
`SDSPI_RSP_BSYWAIT: begin
|
begin // Waiting on R1b, have R1
|
// Waiting on R1b, have R1
|
if (nonzero_out)
|
if (nonzero_out)
|
r_have_resp <= 1'b1;
|
r_have_resp <= 1'b1;
|
ll_cmd_stb <= (r_use_fifo);
|
ll_cmd_stb <= (r_use_fifo);
|
end else if (r_rsp_state == `SDSPI_RSP_GETWORD)
|
end
|
begin // Have R1, waiting on all of R2/R3/R7
|
`SDSPI_RSP_GETWORD: begin
|
r_data_reg <= { r_data_reg[23:0], ll_out_dat };
|
// Have R1, waiting on all of R2/R3/R7
|
|
r_data_reg <= { r_data_reg[23:0],
|
|
ll_out_dat };
|
r_data_fil <= r_data_fil+2'b01;
|
r_data_fil <= r_data_fil+2'b01;
|
if (r_data_fil == 2'b11)
|
if (r_data_fil == 2'b11)
|
begin
|
begin
|
ll_cmd_stb <= (r_use_fifo);
|
ll_cmd_stb <= (r_use_fifo);
|
// r_rsp_state <= 3'h3;
|
// r_rsp_state <= 3'h3;
|
end
|
end end
|
end else if (r_rsp_state == `SDSPI_RSP_WAIT_WHILE_BUSY)
|
`SDSPI_RSP_WAIT_WHILE_BUSY: begin
|
begin // Wait while device is busy writing
|
// Wait while device is busy writing
|
// if (nonzero_out)
|
// if (nonzero_out)
|
// begin
|
// begin
|
// r_data_reg[31:8] <= 24'h00;
|
// r_data_reg[31:8] <= 24'h00;
|
// r_data_reg[7:0] <= ll_out_dat;
|
// r_data_reg[7:0] <= ll_out_dat;
|
// // r_rsp_state <= 3'h6;
|
// // r_rsp_state <= 3'h6;
|
// end
|
// end
|
;
|
end
|
end else if (r_rsp_state == `SDSPI_RSP_RDCOMPLETE)
|
`SDSPI_RSP_RDCOMPLETE: begin
|
begin // Block write command has completed
|
// Block write command has completed
|
ll_cmd_stb <= 1'b0;
|
ll_cmd_stb <= 1'b0;
|
end else if (r_rsp_state == `SDSPI_RSP_WRITING)
|
end
|
begin // We are reading from the device into
|
`SDSPI_RSP_WRITING: begin
|
|
// We are reading from the device into
|
// our FIFO
|
// our FIFO
|
if ((ll_fifo_wr_complete)
|
if ((ll_fifo_wr_complete)
|
// Or ... we receive an error
|
// Or ... we receive an error
|
||((~r_have_start_token)
|
||(r_read_err_token[0]))
|
&&(~ll_out_dat[4])
|
|
&&(ll_out_dat[0])))
|
|
begin
|
begin
|
ll_fifo_wr <= 1'b0;
|
ll_fifo_wr <= 1'b0;
|
ll_cmd_stb <= 1'b0;
|
ll_cmd_stb <= 1'b0;
|
end
|
end end
|
end
|
// `SDSPI_RSP_GETTOKEN:
|
|
default: begin end
|
|
endcase
|
end
|
end
|
|
|
|
if ((r_use_fifo)&&(ll_out_stb))
|
|
r_data_reg <= { 26'h3ffffff, r_data_response_token, r_read_err_token };
|
|
|
if (r_watchdog_err)
|
if (r_watchdog_err)
|
ll_cmd_stb <= 1'b0;
|
ll_cmd_stb <= 1'b0;
|
r_cmd_err<= (r_cmd_err)|(fifo_crc_err)|(r_watchdog_err);
|
r_cmd_err<= (r_cmd_err)|(fifo_crc_err)|(r_watchdog_err)
|
|
|(r_err_token);
|
end else if (r_cmd_busy)
|
end else if (r_cmd_busy)
|
begin
|
begin
|
r_cmd_busy <= (ll_cmd_stb)||(~ll_idle);
|
r_cmd_busy <= (ll_cmd_stb)||(!ll_idle);
|
end else if (cmd_stb)
|
end else if (new_cmd)
|
begin // Command write
|
begin // Command write
|
// Clear the error on any write, whether a commanding
|
// Clear the error on any write, whether a commanding
|
// one or not. -- provided the user requests clearing
|
// one or not. -- provided the user requests clearing
|
// it (by setting the bit high)
|
// it (by setting the bit high)
|
r_cmd_err <= (r_cmd_err)&&(~i_wb_data[15]);
|
r_cmd_err <= (r_cmd_err)&&(!wb_data[15]);
|
// In a similar fashion, we can switch fifos even if
|
// In a similar fashion, we can switch fifos even if
|
// not in the middle of a command
|
// not in the middle of a command
|
r_fifo_id <= i_wb_data[12];
|
r_fifo_id <= wb_data[12];
|
//
|
//
|
// Doesn't matter what this is set to as long as we
|
// Doesn't matter what this is set to as long as we
|
// aren't busy, so we can set it irrelevantly here.
|
// aren't busy, so we can set it irrelevantly here.
|
ll_cmd_dat <= i_wb_data[7:0];
|
ll_cmd_dat <= wb_data[7:0];
|
//
|
//
|
// Note that we only issue a write upon receiving a
|
// Note that we only issue a write upon receiving a
|
// valid command. Such a command is 8 bits, and must
|
// valid command. Such a command is 8 bits, and must
|
// start with its high order bits set to zero and one.
|
// start with its high order bits set to zero and one.
|
// Hence ... we test for that here.
|
// Hence ... we test for that here.
|
if (i_wb_data[7:6] == 2'b01)
|
if (wb_data[7:6] == 2'b01)
|
begin // Issue a command
|
begin // Issue a command
|
//
|
//
|
r_cmd_busy <= 1'b1;
|
r_cmd_busy <= 1'b1;
|
//
|
//
|
ll_cmd_stb <= 1'b1;
|
ll_cmd_stb <= 1'b1;
|
r_cmd_resp <= i_wb_data[9:8];
|
r_cmd_resp <= wb_data[9:8];
|
//
|
//
|
r_cmd_crc_stb <= 1'b1;
|
r_cmd_crc_stb <= 1'b1;
|
//
|
//
|
r_fifo_wr <= i_wb_data[10];
|
r_fifo_wr <= wb_data[10];
|
r_use_fifo <= i_wb_data[11];
|
r_use_fifo <= wb_data[11];
|
//
|
//
|
end else if (i_wb_data[7])
|
end else if (wb_data[7])
|
// If, on the other hand, the command was invalid,
|
// If, on the other hand, the command was invalid,
|
// then it must have been an attempt to read our
|
// then it must have been an attempt to read our
|
// internal configuration. So we'll place that on
|
// internal configuration. So we'll place that on
|
// our data register.
|
// our data register.
|
r_data_reg <= { 8'h00,
|
r_data_reg <= { 8'h00,
|
4'h0, max_lgblklen,
|
4'h0, max_lgblklen,
|
4'h0, r_lgblklen, 1'b0, r_sdspi_clk };
|
4'h0, r_lgblklen, 1'b0, r_sdspi_clk };
|
end else if ((write_stb)&&(i_wb_addr == `SDSPI_DAT_ADDRESS))
|
end else if (new_data) // Data write
|
begin // Data write
|
r_data_reg <= wb_data;
|
r_data_reg <= i_wb_data;
|
|
end
|
|
end
|
end
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
pre_cmd_state <= (ll_cmd_stb)&&(ll_idle);
|
pre_cmd_state <= (ll_cmd_stb)&&(ll_idle);
|
|
|
reg ready_for_response_token;
|
reg ready_for_response_token;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (~r_cmd_busy)
|
if (!r_cmd_busy)
|
ready_for_response_token <= 1'b0;
|
ready_for_response_token <= 1'b0;
|
else if (ll_fifo_rd)
|
else if (ll_fifo_rd)
|
ready_for_response_token <= 1'b1;
|
ready_for_response_token <= 1'b1;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (~r_cmd_busy)
|
if (!r_cmd_busy)
|
r_have_data_response_token <= 1'b0;
|
r_have_data_response_token <= 1'b0;
|
else if ((ll_out_stb)&&(ready_for_response_token)&&(~ll_out_dat[4]))
|
else if ((ll_out_stb)&&(ready_for_response_token)&&(!ll_out_dat[4]))
|
r_have_data_response_token <= 1'b1;
|
r_have_data_response_token <= 1'b1;
|
|
|
reg [2:0] second_rsp_state;
|
reg [2:0] second_rsp_state;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if((r_cmd_resp == `SDSPI_EXPECT_R1)&&(r_use_fifo)&&(r_fifo_wr))
|
if((r_cmd_resp == `SDSPI_EXPECT_R1)&&(r_use_fifo)&&(r_fifo_wr))
|
| Line 415... |
Line 468... |
pre_rsp_state <= (ll_out_stb)&&(r_cmd_sent);
|
pre_rsp_state <= (ll_out_stb)&&(r_cmd_sent);
|
|
|
// Each bit depends upon 8 bits of input
|
// Each bit depends upon 8 bits of input
|
initial r_rsp_state = 3'h0;
|
initial r_rsp_state = 3'h0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (~r_cmd_sent)
|
if (!r_cmd_sent)
|
r_rsp_state <= 3'h0;
|
r_rsp_state <= 3'h0;
|
else if (pre_rsp_state)
|
else if (pre_rsp_state)
|
begin
|
begin
|
if ((r_rsp_state == `SDSPI_RSP_NONE)&&(~ll_out_dat[7]))
|
if ((r_rsp_state == `SDSPI_RSP_NONE)&&(!ll_out_dat[7]))
|
begin
|
begin
|
r_rsp_state <= second_rsp_state;
|
r_rsp_state <= second_rsp_state;
|
end else if (r_rsp_state == `SDSPI_RSP_BSYWAIT)
|
end else if (r_rsp_state == `SDSPI_RSP_BSYWAIT)
|
begin // Waiting on R1b, have R1
|
begin // Waiting on R1b, have R1
|
// R1b never uses the FIFO
|
// R1b never uses the FIFO
|
| Line 460... |
Line 513... |
begin
|
begin
|
// Update our internal configuration parameters, unconnected
|
// Update our internal configuration parameters, unconnected
|
// with the card. These include the speed of the interface,
|
// with the card. These include the speed of the interface,
|
// and the size of the block length to expect as part of a FIFO
|
// and the size of the block length to expect as part of a FIFO
|
// command.
|
// command.
|
if ((cmd_stb)&&(i_wb_data[7:6]==2'b11)&&(~r_data_reg[7])
|
if ((new_cmd)&&(wb_data[7:6]==2'b11)&&(!r_data_reg[7])
|
&&(r_data_reg[15:12]==4'h00))
|
&&(r_data_reg[15:12]==4'h00))
|
begin
|
begin
|
if (|r_data_reg[6:0])
|
if (|r_data_reg[6:0])
|
r_sdspi_clk <= r_data_reg[6:0];
|
r_sdspi_clk <= r_data_reg[6:0];
|
if (|r_data_reg[11:8])
|
if (|r_data_reg[11:8])
|
| Line 473... |
Line 526... |
r_lgblklen <= max_lgblklen;
|
r_lgblklen <= max_lgblklen;
|
end
|
end
|
|
|
assign need_reset = 1'b0;
|
assign need_reset = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
case(i_wb_addr)
|
case(wb_addr)
|
`SDSPI_CMD_ADDRESS:
|
`SDSPI_CMD_ADDRESS:
|
o_wb_data <= { need_reset, 11'h00,
|
o_wb_data <= { need_reset, 11'h00,
|
3'h0, fifo_crc_err,
|
2'h0, r_err_token, fifo_crc_err,
|
r_cmd_err, r_cmd_busy, 1'b0, r_fifo_id,
|
r_cmd_err, r_cmd_busy, 1'b0, r_fifo_id,
|
r_use_fifo, r_fifo_wr, r_cmd_resp,
|
r_use_fifo, r_fifo_wr, r_cmd_resp,
|
r_last_r_one };
|
r_last_r_one };
|
`SDSPI_DAT_ADDRESS:
|
`SDSPI_DAT_ADDRESS:
|
o_wb_data <= r_data_reg;
|
o_wb_data <= r_data_reg;
|
| Line 495... |
Line 548... |
|
|
initial q_busy = 1'b1;
|
initial q_busy = 1'b1;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
q_busy <= r_cmd_busy;
|
q_busy <= r_cmd_busy;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
o_int <= (~r_cmd_busy)&&(q_busy);
|
o_int <= (!r_cmd_busy)&&(q_busy);
|
|
|
assign o_wb_stall = 1'b0;
|
assign o_wb_stall = 1'b0;
|
|
|
//
|
//
|
// Let's work with our FIFO memory here ...
|
// Let's work with our FIFO memory here ...
|
//
|
//
|
//
|
//
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
begin
|
begin
|
if ((write_stb)&&(i_wb_addr == `SDSPI_CMD_ADDRESS))
|
if ((write_stb)&&(wb_addr == `SDSPI_CMD_ADDRESS))
|
begin // Command write
|
begin // Command write
|
// Clear the read/write address
|
// Clear the read/write address
|
fifo_wb_addr <= {(LGFIFOLN){1'b0}};
|
fifo_wb_addr <= {(LGFIFOLN){1'b0}};
|
end else if ((wb_stb)&&(i_wb_addr[1]))
|
end else if ((wb_stb)&&(wb_addr[1]))
|
begin // On read or write, of either FIFO,
|
begin // On read or write, of either FIFO,
|
// we increase our pointer
|
// we increase our pointer
|
fifo_wb_addr <= fifo_wb_addr + 1;
|
fifo_wb_addr <= fifo_wb_addr + 1;
|
// And let ourselves know we need to update ourselves
|
// And let ourselves know we need to update ourselves
|
// on the next clock
|
// on the next clock
|
| Line 523... |
Line 576... |
// Prepare reading of the FIFO for the WB bus read
|
// Prepare reading of the FIFO for the WB bus read
|
// Memory read #1
|
// Memory read #1
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
begin
|
begin
|
fifo_a_reg <= {
|
fifo_a_reg <= {
|
fifo_a_mem[{ fifo_wb_addr, 2'b00 }],
|
fifo_a_mem_0[ fifo_wb_addr ],
|
fifo_a_mem[{ fifo_wb_addr, 2'b01 }],
|
fifo_a_mem_1[ fifo_wb_addr ],
|
fifo_a_mem[{ fifo_wb_addr, 2'b10 }],
|
fifo_a_mem_2[ fifo_wb_addr ],
|
fifo_a_mem[{ fifo_wb_addr, 2'b11 }] };
|
fifo_a_mem_3[ fifo_wb_addr ] };
|
fifo_b_reg <= {
|
fifo_b_reg <= {
|
fifo_b_mem[{ fifo_wb_addr, 2'b00 }],
|
fifo_b_mem_0[ fifo_wb_addr ],
|
fifo_b_mem[{ fifo_wb_addr, 2'b01 }],
|
fifo_b_mem_1[ fifo_wb_addr ],
|
fifo_b_mem[{ fifo_wb_addr, 2'b10 }],
|
fifo_b_mem_2[ fifo_wb_addr ],
|
fifo_b_mem[{ fifo_wb_addr, 2'b11 }] };
|
fifo_b_mem_3[ fifo_wb_addr ] };
|
end
|
end
|
|
|
// Okay, now ... writing our FIFO ...
|
// Okay, now ... writing our FIFO ...
|
reg pre_fifo_addr_inc_rd;
|
reg pre_fifo_addr_inc_rd;
|
reg pre_fifo_addr_inc_wr;
|
reg pre_fifo_addr_inc_wr;
|
initial pre_fifo_addr_inc_rd = 1'b0;
|
initial pre_fifo_addr_inc_rd = 1'b0;
|
initial pre_fifo_addr_inc_wr = 1'b0;
|
initial pre_fifo_addr_inc_wr = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
pre_fifo_addr_inc_wr <= ((ll_fifo_wr)&&(ll_out_stb)&&(r_have_start_token));
|
pre_fifo_addr_inc_wr <= ((ll_fifo_wr)&&(ll_out_stb)
|
|
&&(r_have_start_token));
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
pre_fifo_addr_inc_rd <= ((ll_fifo_rd)&&(ll_cmd_stb)&&(ll_idle));//&&(ll_fifo_pkt_state[2:0]!=3'b000));
|
pre_fifo_addr_inc_rd <= ((ll_fifo_rd)&&(ll_cmd_stb)&&(ll_idle));
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
begin
|
begin
|
// if ((write_stb)&&(i_wb_addr == `SDSPI_CMD_ADDRESS)&&(i_wb_data[11]))
|
if (!r_cmd_busy)
|
// ll_fifo_addr <= {(LGFIFOLN+2){1'b0}};
|
|
if (~r_cmd_busy)
|
|
ll_fifo_addr <= {(LGFIFOLN+2){1'b0}};
|
ll_fifo_addr <= {(LGFIFOLN+2){1'b0}};
|
else if ((pre_fifo_addr_inc_wr)||(pre_fifo_addr_inc_rd))
|
else if ((pre_fifo_addr_inc_wr)||(pre_fifo_addr_inc_rd))
|
ll_fifo_addr <= ll_fifo_addr + 1;
|
ll_fifo_addr <= ll_fifo_addr + 1;
|
end
|
end
|
|
|
// Look for that start token
|
//
|
|
// Look for that start token. This will be present when reading from
|
|
// the device into the FIFO.
|
|
//
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (~r_cmd_busy)
|
if (!r_cmd_busy)
|
r_have_start_token <= 1'b0;
|
r_have_start_token <= 1'b0;
|
else if ((ll_fifo_wr)&&(ll_out_stb)&&(ll_out_dat==8'hfe))
|
else if ((ll_fifo_wr)&&(ll_out_stb)&&(ll_out_dat==8'hfe))
|
r_have_start_token <= 1'b1;
|
r_have_start_token <= 1'b1;
|
|
always @(posedge i_clk)
|
|
if (!r_cmd_busy)
|
|
r_read_err_token <= 4'h0;
|
|
else if ((ll_fifo_wr)&&(ll_out_stb)&&(!r_have_start_token)
|
|
&&(ll_out_dat[7:4]==4'h0))
|
|
r_read_err_token <= ll_out_dat[3:0];
|
|
always @(posedge i_clk) // Look for a response to our writing
|
|
if (!r_cmd_busy)
|
|
r_data_response_token <= 2'b00;
|
|
else if ((ready_for_response_token)
|
|
&&(!ll_out_dat[4])&&(ll_out_dat[0]))
|
|
r_data_response_token <= ll_out_dat[3:2];
|
|
initial r_err_token = 1'b0;
|
|
always @(posedge i_clk)
|
|
if (ll_fifo_rd)
|
|
r_err_token <= (r_err_token)|(r_read_err_token[0]);
|
|
else if (ll_fifo_wr)
|
|
r_err_token <= (r_err_token)|
|
|
((|r_data_response_token)&&(r_data_response_token[1]));
|
|
else if (cmd_stb)
|
|
// Clear the error on any write with the bit high
|
|
r_err_token <= (r_err_token)&&(!i_wb_data[16])
|
|
&&(!i_wb_data[15]);
|
|
|
reg last_fifo_byte;
|
reg last_fifo_byte;
|
initial last_fifo_byte = 1'b0;
|
initial last_fifo_byte = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (ll_fifo_wr)
|
if (ll_fifo_wr)
|
| Line 580... |
Line 658... |
//
|
//
|
reg pre_fifo_a_wr, pre_fifo_b_wr, pre_fifo_crc_a, pre_fifo_crc_b,
|
reg pre_fifo_a_wr, pre_fifo_b_wr, pre_fifo_crc_a, pre_fifo_crc_b,
|
clear_fifo_crc;
|
clear_fifo_crc;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
begin
|
begin
|
pre_fifo_a_wr <= (ll_fifo_wr)&&(ll_out_stb)&&(~r_fifo_id)&&(ll_fifo_wr_state == 2'b00);
|
pre_fifo_a_wr <= (ll_fifo_wr)&&(ll_out_stb)
|
pre_fifo_b_wr <= (ll_fifo_wr)&&(ll_out_stb)&&( r_fifo_id)&&(ll_fifo_wr_state == 2'b00);
|
&&(!r_fifo_id)&&(ll_fifo_wr_state == 2'b00);
|
fifo_wr_crc_stb <= (ll_fifo_wr)&&(ll_out_stb)&&(ll_fifo_wr_state == 2'b00)&&(r_have_start_token);
|
pre_fifo_b_wr <= (ll_fifo_wr)&&(ll_out_stb)
|
pre_fifo_crc_a<= (ll_fifo_wr)&&(ll_out_stb)&&(ll_fifo_wr_state == 2'b01);
|
&&( r_fifo_id)&&(ll_fifo_wr_state == 2'b00);
|
pre_fifo_crc_b<= (ll_fifo_wr)&&(ll_out_stb)&&(ll_fifo_wr_state == 2'b10);
|
fifo_wr_crc_stb <= (ll_fifo_wr)&&(ll_out_stb)
|
clear_fifo_crc <= (cmd_stb)&&(i_wb_data[15]);
|
&&(ll_fifo_wr_state == 2'b00)&&(r_have_start_token);
|
end
|
pre_fifo_crc_a<= (ll_fifo_wr)&&(ll_out_stb)
|
|
&&(ll_fifo_wr_state == 2'b01);
|
|
pre_fifo_crc_b<= (ll_fifo_wr)&&(ll_out_stb)
|
|
&&(ll_fifo_wr_state == 2'b10);
|
|
clear_fifo_crc <= (new_cmd)&&(wb_data[15]);
|
|
end
|
|
|
|
reg fifo_a_wr, fifo_b_wr;
|
|
reg [3:0] fifo_a_wr_mask, fifo_b_wr_mask;
|
|
reg [(LGFIFOLN-1):0] fifo_a_wr_addr, fifo_b_wr_addr;
|
|
reg [31:0] fifo_a_wr_data, fifo_b_wr_data;
|
|
|
initial fifo_crc_err = 1'b0;
|
initial fifo_crc_err = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
begin // One and only memory write allowed
|
begin // One and only memory write allowed
|
if ((write_stb)&&(i_wb_addr[1:0]==2'b10))
|
fifo_a_wr <= 1'b0;
|
{fifo_a_mem[{ fifo_wb_addr, 2'b00 }],
|
fifo_a_wr_data <= { ll_out_dat, ll_out_dat, ll_out_dat, ll_out_dat };
|
fifo_a_mem[{ fifo_wb_addr, 2'b01 }],
|
if ((write_stb)&&(wb_addr[1:0]==2'b10))
|
fifo_a_mem[{ fifo_wb_addr, 2'b10 }],
|
begin
|
fifo_a_mem[{ fifo_wb_addr, 2'b11 }] }
|
fifo_a_wr <= 1'b1;
|
<= i_wb_data;
|
fifo_a_wr_mask <= 4'b1111;
|
else if (pre_fifo_a_wr)
|
fifo_a_wr_addr <= fifo_wb_addr;
|
fifo_a_mem[{ ll_fifo_addr }] <= ll_out_dat;
|
fifo_a_wr_data <= wb_data;
|
|
end else if (pre_fifo_a_wr)
|
if ((write_stb)&&(i_wb_addr[1:0]==2'b11))
|
begin
|
{fifo_b_mem[{fifo_wb_addr, 2'b00 }],
|
fifo_a_wr <= 1'b1;
|
fifo_b_mem[{ fifo_wb_addr, 2'b01 }],
|
fifo_a_wr_addr <= ll_fifo_addr[(LGFIFOLN+1):2];
|
fifo_b_mem[{ fifo_wb_addr, 2'b10 }],
|
case(ll_fifo_addr[1:0])
|
fifo_b_mem[{ fifo_wb_addr, 2'b11 }] }
|
2'b00: fifo_a_wr_mask <= 4'b0001;
|
<= i_wb_data;
|
2'b01: fifo_a_wr_mask <= 4'b0010;
|
else if (pre_fifo_b_wr)
|
2'b10: fifo_a_wr_mask <= 4'b0100;
|
fifo_b_mem[{ ll_fifo_addr }] <= ll_out_dat;
|
2'b11: fifo_a_wr_mask <= 4'b1000;
|
|
endcase
|
|
end
|
|
|
|
if ((fifo_a_wr)&&(fifo_a_wr_mask[0]))
|
|
fifo_a_mem_0[fifo_a_wr_addr] <= fifo_a_wr_data[7:0];
|
|
if ((fifo_a_wr)&&(fifo_a_wr_mask[1]))
|
|
fifo_a_mem_1[fifo_a_wr_addr] <= fifo_a_wr_data[15:8];
|
|
if ((fifo_a_wr)&&(fifo_a_wr_mask[2]))
|
|
fifo_a_mem_2[fifo_a_wr_addr] <= fifo_a_wr_data[23:16];
|
|
if ((fifo_a_wr)&&(fifo_a_wr_mask[3]))
|
|
fifo_a_mem_3[fifo_a_wr_addr] <= fifo_a_wr_data[31:24];
|
|
|
|
fifo_b_wr <= 1'b0;
|
|
fifo_b_wr_data <= { ll_out_dat, ll_out_dat, ll_out_dat, ll_out_dat };
|
|
if ((write_stb)&&(wb_addr[1:0]==2'b11))
|
|
begin
|
|
fifo_b_wr <= 1'b1;
|
|
fifo_b_wr_mask <= 4'b1111;
|
|
fifo_b_wr_addr <= fifo_wb_addr;
|
|
fifo_b_wr_data <= wb_data;
|
|
end else if (pre_fifo_b_wr)
|
|
begin
|
|
fifo_b_wr <= 1'b1;
|
|
fifo_b_wr_addr <= ll_fifo_addr[(LGFIFOLN+1):2];
|
|
case(ll_fifo_addr[1:0])
|
|
2'b00: fifo_b_wr_mask <= 4'b0001;
|
|
2'b01: fifo_b_wr_mask <= 4'b0010;
|
|
2'b10: fifo_b_wr_mask <= 4'b0100;
|
|
2'b11: fifo_b_wr_mask <= 4'b1000;
|
|
endcase
|
|
end
|
|
|
|
if ((fifo_b_wr)&&(fifo_b_wr_mask[0]))
|
|
fifo_b_mem_0[fifo_b_wr_addr] <= fifo_b_wr_data[7:0];
|
|
if ((fifo_b_wr)&&(fifo_b_wr_mask[1]))
|
|
fifo_b_mem_1[fifo_b_wr_addr] <= fifo_b_wr_data[15:8];
|
|
if ((fifo_b_wr)&&(fifo_b_wr_mask[2]))
|
|
fifo_b_mem_2[fifo_b_wr_addr] <= fifo_b_wr_data[23:16];
|
|
if ((fifo_b_wr)&&(fifo_b_wr_mask[3]))
|
|
fifo_b_mem_3[fifo_b_wr_addr] <= fifo_b_wr_data[31:24];
|
|
|
if (~r_cmd_busy)
|
if (!r_cmd_busy)
|
ll_fifo_wr_complete <= 1'b0;
|
ll_fifo_wr_complete <= 1'b0;
|
|
|
if (~r_cmd_busy)
|
if (!r_cmd_busy)
|
ll_fifo_wr_state <= 2'b00;
|
ll_fifo_wr_state <= 2'b00;
|
else if ((pre_fifo_a_wr)||(pre_fifo_b_wr))
|
else if ((pre_fifo_a_wr)||(pre_fifo_b_wr))
|
ll_fifo_wr_state <= (last_fifo_byte)? 2'b01:2'b00;
|
ll_fifo_wr_state <= (last_fifo_byte)? 2'b01:2'b00;
|
|
|
if (pre_fifo_crc_a)
|
if (pre_fifo_crc_a)
|
| Line 632... |
Line 760... |
fifo_crc_err <= 1'b0;
|
fifo_crc_err <= 1'b0;
|
end
|
end
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
begin // Second memory read, this time for the FIFO
|
begin // Second memory read, this time for the FIFO
|
fifo_a_byte <= fifo_a_mem[ ll_fifo_addr ];
|
case(ll_fifo_addr[1:0])
|
fifo_b_byte <= fifo_b_mem[ ll_fifo_addr ];
|
2'b00: begin
|
|
fifo_a_byte<=fifo_a_mem_0[ll_fifo_addr[(LGFIFOLN+1):2]];
|
|
fifo_b_byte<=fifo_b_mem_0[ll_fifo_addr[(LGFIFOLN+1):2]];
|
|
end
|
|
2'b01: begin
|
|
fifo_a_byte<=fifo_a_mem_1[ll_fifo_addr[(LGFIFOLN+1):2]];
|
|
fifo_b_byte<=fifo_b_mem_1[ll_fifo_addr[(LGFIFOLN+1):2]];
|
|
end
|
|
2'b10: begin
|
|
fifo_a_byte<=fifo_a_mem_2[ll_fifo_addr[(LGFIFOLN+1):2]];
|
|
fifo_b_byte<=fifo_b_mem_2[ll_fifo_addr[(LGFIFOLN+1):2]];
|
|
end
|
|
2'b11: begin
|
|
fifo_a_byte<=fifo_a_mem_3[ll_fifo_addr[(LGFIFOLN+1):2]];
|
|
fifo_b_byte<=fifo_b_mem_3[ll_fifo_addr[(LGFIFOLN+1):2]];
|
|
end
|
|
endcase
|
end
|
end
|
|
|
reg [(LGFIFOLN-1):0] r_blklimit;
|
reg [(LGFIFOLN-1):0] r_blklimit;
|
wire [(LGFIFOLN+1):0] w_blklimit;
|
wire [(LGFIFOLN+1):0] w_blklimit;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
r_blklimit[(LGFIFOLN-1):0] = (1<<r_lgblklen)-1;
|
r_blklimit[(LGFIFOLN-1):0] <= (1<<r_lgblklen)-1;
|
assign w_blklimit = { r_blklimit, 2'b11 };
|
assign w_blklimit = { r_blklimit, 2'b11 };
|
|
|
// Package the FIFO reads up into a packet
|
// Package the FIFO reads up into a packet
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
begin
|
begin
|
| Line 693... |
Line 837... |
begin
|
begin
|
// Idle the channel
|
// Idle the channel
|
ll_fifo_rd_complete <= 1'b1;
|
ll_fifo_rd_complete <= 1'b1;
|
fifo_byte <= 8'hff;
|
fifo_byte <= 8'hff;
|
end
|
end
|
end else if ((write_stb)&&(i_wb_addr == `SDSPI_CMD_ADDRESS))
|
end else if ((write_stb)&&(wb_addr == `SDSPI_CMD_ADDRESS))
|
begin
|
begin
|
ll_fifo_pkt_state <= 3'h0;
|
ll_fifo_pkt_state <= 3'h0;
|
ll_fifo_rd_complete <= 1'b0;
|
ll_fifo_rd_complete <= 1'b0;
|
fifo_byte <= (i_wb_data[12]) ? fifo_b_byte : fifo_a_byte;
|
fifo_byte <= (wb_data[12]) ? fifo_b_byte : fifo_a_byte;
|
fifo_rd_crc_stb <= 1'b1;
|
fifo_rd_crc_stb <= 1'b1;
|
end else begin // Packet state is IDLE (clear the CRC registers)
|
end else begin // Packet state is IDLE (clear the CRC registers)
|
ll_fifo_pkt_state <= 3'b111;
|
ll_fifo_pkt_state <= 3'b111;
|
ll_fifo_rd_complete <= 1'b1;
|
ll_fifo_rd_complete <= 1'b1;
|
end
|
end
|
end
|
end
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
begin
|
begin
|
if (~ll_fifo_wr)
|
if (!ll_fifo_wr)
|
fifo_wr_crc_reg <= 16'h00;
|
fifo_wr_crc_reg <= 16'h00;
|
else if (fifo_wr_crc_stb)
|
else if (fifo_wr_crc_stb)
|
begin
|
begin
|
fifo_wr_crc_reg[15:8] <=fifo_wr_crc_reg[15:8]^ll_out_dat;
|
fifo_wr_crc_reg[15:8] <=fifo_wr_crc_reg[15:8]^ll_out_dat;
|
fifo_wr_crc_count <= 4'h8;
|
fifo_wr_crc_count <= 4'h8;
|
| Line 726... |
Line 870... |
end
|
end
|
end
|
end
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
begin
|
begin
|
if (~r_cmd_busy)
|
if (!r_cmd_busy)
|
begin
|
begin
|
fifo_rd_crc_reg <= 16'h00;
|
fifo_rd_crc_reg <= 16'h00;
|
fifo_rd_crc_count <= 4'h0;
|
fifo_rd_crc_count <= 4'h0;
|
end else if (fifo_rd_crc_stb)
|
end else if (fifo_rd_crc_stb)
|
begin
|
begin
|
| Line 751... |
Line 895... |
// Calculate a CRC for the command section of our output
|
// Calculate a CRC for the command section of our output
|
//
|
//
|
initial r_cmd_crc_ff = 1'b0;
|
initial r_cmd_crc_ff = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
begin
|
begin
|
if (~r_cmd_busy)
|
if (!r_cmd_busy)
|
begin
|
begin
|
r_cmd_crc <= 8'h00;
|
r_cmd_crc <= 8'h00;
|
r_cmd_crc_cnt <= 4'hf;
|
r_cmd_crc_cnt <= 4'hf;
|
r_cmd_crc_ff <= 1'b0;
|
r_cmd_crc_ff <= 1'b0;
|
end else if (~r_cmd_crc_cnt[3])
|
end else if (!r_cmd_crc_cnt[3])
|
begin
|
begin
|
r_cmd_crc_cnt <= r_cmd_crc_cnt - 4'h1;
|
r_cmd_crc_cnt <= r_cmd_crc_cnt - 4'h1;
|
if (r_cmd_crc[7])
|
if (r_cmd_crc[7])
|
r_cmd_crc <= { r_cmd_crc[6:0], 1'b0 } ^ 8'h12;
|
r_cmd_crc <= { r_cmd_crc[6:0], 1'b0 } ^ 8'h12;
|
else
|
else
|
| Line 782... |
Line 926... |
// we'll have an error indication.
|
// we'll have an error indication.
|
//
|
//
|
initial r_watchdog = 26'h3ffffff;
|
initial r_watchdog = 26'h3ffffff;
|
initial r_watchdog_err = 1'b0;
|
initial r_watchdog_err = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (~r_cmd_busy)
|
if (!r_cmd_busy)
|
r_watchdog_err <= 1'b0;
|
r_watchdog_err <= 1'b0;
|
else if (r_watchdog == 0)
|
else if (r_watchdog == 0)
|
r_watchdog_err <= 1'b1;
|
r_watchdog_err <= 1'b1;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (~r_cmd_busy)
|
if (!r_cmd_busy)
|
r_watchdog <= 26'h3fffff;
|
r_watchdog <= 26'h3fffff;
|
else if (|r_watchdog)
|
else if (|r_watchdog)
|
r_watchdog <= r_watchdog - 26'h1;
|
r_watchdog <= r_watchdog - 26'h1;
|
|
|
assign o_debug = { ((ll_cmd_stb)&&(ll_idle))||(ll_out_stb),
|
assign o_debug = { ((ll_cmd_stb)&&(ll_idle))||(ll_out_stb),
|
| Line 799... |
Line 943... |
o_cs_n, o_sck, o_mosi, i_miso, // 4'h
|
o_cs_n, o_sck, o_mosi, i_miso, // 4'h
|
r_cmd_state, i_bus_grant, // 4'h
|
r_cmd_state, i_bus_grant, // 4'h
|
r_rsp_state, r_cmd_busy, // 4'h
|
r_rsp_state, r_cmd_busy, // 4'h
|
ll_cmd_dat, // 8'b
|
ll_cmd_dat, // 8'b
|
ll_out_dat }; // 8'b
|
ll_out_dat }; // 8'b
|
|
|
|
// Make verilator happy
|
|
// verilator lint_off UNUSED
|
|
wire unused;
|
|
assign unused = i_wb_cyc;
|
|
// verilator lint_on UNUSED
|
endmodule
|
endmodule
|
|
|
|
|
No newline at end of file
|
No newline at end of file
|
