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https://opencores.org/ocsvn/simu_mem/simu_mem/trunk
[/] [simu_mem/] [trunk/] [rtl/] [vhdl/] [ZBT_RAM.vhd] - Diff between revs 5 and 8
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| Rev 5 |
Rev 8 |
| Line 162... |
Line 162... |
(state = read) OR
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(state = read) OR
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(state = dummy_read) OR
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(state = dummy_read) OR
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(state = write_abort)) AND (CKE_n = '0')) THEN
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(state = write_abort)) AND (CKE_n = '0')) THEN
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A_delayed_2 <= A_delayed_1;
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A_delayed_2 <= A_delayed_1;
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ELSIF (ADV_delayed = '1') AND (CKE_n = '0') THEN
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ELSIF (ADV_delayed = '1') AND (CKE_n = '0') THEN
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IF (A_delayed_2 MOD (D_width / 9) < D_width / 9 - 1) THEN
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IF (A_delayed_2 MOD 4 < 3) THEN
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A_delayed_2 <= A_delayed_2 + 1;
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A_delayed_2 <= A_delayed_2 + 1;
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ELSE
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ELSE
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A_delayed_2 <= A_delayed_1;
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A_delayed_2 <= A_delayed_1;
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END IF;
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END IF;
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END IF;
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END IF;
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