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[/] [socgen/] [trunk/] [Projects/] [digilentinc.com/] [Nexys2/] [ip/] [jtag/] [rtl/] [verilog/] [syn/] [jtag_tap.v] - Diff between revs 133 and 135

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Rev 133 Rev 135
Line 62... Line 62... 
module cde_jtag_tap
 
module cde_jtag_tap
 
#(parameter  CHIP_ID_VAL=32'h00000000 )
 
#(parameter  CHIP_ID_VAL=32'h00000000 )
 
(
 
(
 
 
 
 
 
input   wire           tdo_i,
 
input   wire           tdo_i,
 
 
 
 
 
 
 
 
 
 
 
 input wire  tclk_pad_in,
 
 
 
 input wire  tms_pad_in,
 
 
 
 input wire  tdi_pad_in,
 
 
 
 input wire  trst_n_pad_in,
 
 
 
 output wire tdo_pad_out,
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
output  wire           shiftcapture_dr_clk_o,
 
output  wire           shiftcapture_dr_clk_o,
 
output  wire           tdi_o,
 
output  wire           tdi_o,
 
output  wire           test_logic_reset_o,
 
output  wire           test_logic_reset_o,
 
output  wire           shift_dr_o,
 
output  wire           shift_dr_o,
 
output  wire           capture_dr_o,
 
output  wire           capture_dr_o,

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