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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [T6502/] [rtl/] [xml/] [T6502_def.design.xml] - Diff between revs 134 and 135

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`// You should have received a copy of the GNU Lesser General //`	`// You should have received a copy of the GNU Lesser General //`
`// Public License along with this source; if not, download it //`	`// Public License along with this source; if not, download it //`
`// from http://www.opencores.org/lgpl.shtml //`	`// from http://www.opencores.org/lgpl.shtml //`
`// //`	`// //`
`-->`	`-->`

`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`	`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
`xmlns:socgen="http://opencores.org"`	`xmlns:socgen="http://opencores.org"`
`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`	`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`	`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`

`opencores.org`	`opencores.org`
`Mos6502`	`Mos6502`
`T6502`	`T6502`
`def.design`	`def.design`






`mem_addr`	`mem_addr`
`cpu_addr`	`cpu_addr`
`wire`	`wire`
`CPU_ADD-10`	`CPU_ADD-10`




	`data_addr`
	`wire`
	`RAM_ADD1`































	`uart`






	`ps2`





	`vga`







`mem`





	`mem`




`ext_mem`







	`ext_mem`










`io_reg`







	`io_reg`






`prog_rom_mem`






`sh_prog_rom_mem`	`prog_rom_mem`






`data`	`sh_prog_rom_mem`






	`data`







`cpu`






	`cpu`






`syn_jtag`






`jtag`	`syn_jtag`






	`jtag`


















`clk`














	`clk`














`reset`








	`reset`











`mem_addr`






`mem_addr`	`mem_addr`






	`mem_addr`






`ext_rdata`





`prog_rom_mem_rdata`




`sh_prog_rom_mem_rdata`	`ext_rdata`





`gpio_0_out`	`prog_rom_mem_rdata`





	`sh_prog_rom_mem_rdata`




	`gpio_0_out`





`gpio_0_oe`






	`gpio_0_oe`







`gpio_0_in`





`gpio_1_out`





	`gpio_0_in`





	`gpio_1_out`





`gpio_1_oe`






	`gpio_1_oe`






`gpio_1_in`






	`gpio_1_in`





`cts_pad_in`





`rts_pad_out`





	`cts_pad_in`





	`rts_pad_out`














`alu_status`






`enable`	`alu_status`








`pg0_add`	`enable`








	`pg0_add`





`pg0_rd`





`pg0_wr`





`cpu_pg0_data`	`pg0_rd`





`vector`	`pg0_wr`






	`cpu_pg0_data`





`nmi_in`	`vector`







	`nmi_in`







`mem_wdata`






	`mem_wdata`





`rx_irq`





`tx_irq`





`ps2_data_avail`	`rx_irq`





	`tx_irq`





`io_module_pic_irq_in`	`ps2_data_avail`





`io_module_vic_irq_in`





`timer_irq`	`io_module_pic_irq_in`





`ext_addr`	`io_module_vic_irq_in`





	`timer_irq`





`ext_wdata`	`ext_addr`






`ext_ub`	`ext_wdata`






`ext_lb`	`ext_ub`






`ext_rd`	`ext_lb`





`ext_stb`





`ext_wr`	`ext_rd`





`ext_cs`	`ext_stb`





`ext_wait`	`ext_wr`





	`ext_cs`





	`ext_wait`







`mem_rd`






`mem_wr`	`mem_rd`






`pg0_rd`	`mem_wr`






`pg0_wr`	`pg0_rd`






`ps2_data_avail`	`pg0_wr`






`rx_irq`	`ps2_data_avail`






`timer_irq`	`rx_irq`






`tx_irq`	`timer_irq`






`mem_addr`	`tx_irq`






`pg0_add`	`mem_addr`





`mem_rdata`





	`pg0_add`





`mem_wdata`	`mem_rdata`






	`mem_wdata`






`ext_irq_in`






`mem_cs`	`ext_irq_in`





`pg00_ram_l_wr`





	`mem_cs`






`cpu_pg0_data`	`cpu_pg0_data`






`io_module_pic_irq_in`	`io_module_pic_irq_in`






`io_module_vic_irq_in`	`io_module_vic_irq_in`




























`jsp_data_out`	`jsp_data_out`







`wb_jsp_dat_i`	`wb_jsp_dat_i`






`biu_wr_strobe`	`biu_wr_strobe`






`wb_jsp_stb_i`	`wb_jsp_stb_i`
















`io_module`	`io_module`


`0`	`0`
`8`	`8`
`UART_PRESCALE`	`UART_PRESCALE`
`UART_PRE_SIZE`	`UART_PRE_SIZE`
`UART_DIV`	`UART_DIV`







`cpu`	`cpu`


`VEC_TABLE`	`VEC_TABLE`
`PROG_ROM_ADD`	`PROG_ROM_ADD`
`PROG_ROM_WORDS`	`PROG_ROM_WORDS`






`micro_bus`	`micro_bus`


`CPU_ADD`	`CPU_ADD`
`SPLIT_CH0_BITS`	`SPLIT_CH0_BITS`
`SPLIT_CH0_MATCH`	`SPLIT_CH0_MATCH`
`SPLIT_CH1_BITS`	`SPLIT_CH1_BITS`
`SPLIT_CH1_MATCH`	`SPLIT_CH1_MATCH`
`SPLIT_CH2_BITS`	`SPLIT_CH2_BITS`
`SPLIT_CH2_MATCH`	`SPLIT_CH2_MATCH`
`SPLIT_CH3_BITS`	`SPLIT_CH3_BITS`
`SPLIT_CH3_MATCH`	`SPLIT_CH3_MATCH`
`SPLIT_CH4_BITS`	`SPLIT_CH4_BITS`
`SPLIT_CH4_MATCH`	`SPLIT_CH4_MATCH`
`SPLIT_CH5_BITS`	`SPLIT_CH5_BITS`
`SPLIT_CH5_MATCH`	`SPLIT_CH5_MATCH`







`boot_rom`	`boot_rom`


`BOOT_ROM_WIDTH`	`BOOT_ROM_WIDTH`
`ROM_ADD`	`ROM_ADD`
`ROM_WORDS`	`ROM_WORDS`
`ROM_WRITETHRU`	`ROM_WRITETHRU`







`sh_prog_rom`	`sh_prog_rom`


`BOOT_ROM_WIDTH`	`BOOT_ROM_WIDTH`
`PROG_ROM_ADD`	`PROG_ROM_ADD`
`PROG_ROM_WORDS`	`PROG_ROM_WORDS`
`ROM_WRITETHRU`	`ROM_WRITETHRU`




`data_sram`	`data_sram`


`RAM_ADD`	`RAM_ADD`
`RAM_WORDS`	`RAM_WORDS`




`ctrl`	`ctrl`


`VEC_TABLE`	`VEC_TABLE`





`adv_dbg`	`adv_dbg`






`jtag_sync`	`jtag_sync`













Line 781...	Line 788...

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [T6502/] [rtl/] [xml/] [T6502_def.design.xml] - Diff between revs 134 and 135