| Line 25... |
Line 25... |
// You should have received a copy of the GNU Lesser General //
|
// You should have received a copy of the GNU Lesser General //
|
// Public License along with this source; if not, download it //
|
// Public License along with this source; if not, download it //
|
// from http://www.opencores.org/lgpl.shtml //
|
// from http://www.opencores.org/lgpl.shtml //
|
// //
|
// //
|
-->
|
-->
|
|
|
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
|
xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
|
xmlns:socgen="http://opencores.org"
|
xmlns:socgen="http://opencores.org"
|
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
|
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
|
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
|
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
|
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
|
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
|
|
|
opencores.org
|
opencores.org
|
Mos6502
|
Mos6502
|
T6502
|
T6502
|
def default
|
def
|
|
|
|
|
|
|
slave_clk
|
slave_clk
|
|
|
|
|
|
|
|
|
|
|
clk
|
|
clk
|
clk
|
|
clk
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
slave_reset
|
|
|
|
|
|
|
|
|
|
|
|
reset
|
|
reset
|
|
|
|
|
|
|
|
|
|
|
slave_reset
|
|
|
|
|
|
|
|
|
|
|
|
|
|
reset
|
|
reset
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
jtag
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
shiftcapture_dr_clk
|
|
jtag_shiftcapture_dr_clk
|
|
|
|
|
|
|
|
|
|
test_logic_reset
|
|
jtag_test_logic_reset
|
|
|
|
|
jtag
|
|
|
capture_dr
|
|
jtag_capture_dr
|
|
|
|
|
|
|
shiftcapture_dr_clk
|
shift_dr
|
jtag_shiftcapture_dr_clk
|
jtag_shift_dr
|
|
|
|
|
|
|
|
update_dr_clk
|
|
jtag_update_dr_clk
|
|
|
|
|
|
|
test_logic_reset
|
|
jtag_test_logic_reset
|
|
|
|
|
|
|
|
capture_dr
|
tdi
|
jtag_capture_dr
|
jtag_tdi
|
|
|
|
|
|
|
shift_dr
|
tdo
|
jtag_shift_dr
|
jtag_tdo
|
|
|
|
|
|
|
update_dr_clk
|
select
|
jtag_update_dr_clk
|
jtag_select
|
|
|
|
|
|
|
|
|
|
|
tdi
|
|
jtag_tdi
|
|
|
|
|
|
|
|
tdo
|
|
jtag_tdo
|
|
|
|
|
|
|
|
select
|
|
jtag_select
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
gen_verilog
|
|
104.0
|
|
none
|
|
:*common:*
|
|
tools/verilog/gen_verilog
|
|
|
|
|
|
destination
|
|
T6502_def
|
|
|
|
|
|
|
|
|
|
|
|
|
gen_verilog
|
|
104.0
|
|
none
|
|
common
|
|
./tools/verilog/gen_verilog
|
|
|
|
|
|
destination
|
|
T6502_def
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
fs-common
|
|
|
|
|
|
|
BOOT_ROM_WIDTH16
|
../verilog/top.rtl
|
ROM_WRITETHRU0
|
verilogSourcefragment
|
ADDR11
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Hierarchical
|
|
|
|
|
|
|
|
|
|
|
|
|
fs-sim
|
|
|
|
|
|
|
|
../verilog/copyright.v
|
|
verilogSourceinclude
|
|
|
|
|
|
|
|
|
|
../verilog/common/T6502_def
|
|
verilogSourcemodule
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Hierarchical
|
|
Hierarchical
|
|
|
|
|
fs-syn
|
|
|
|
|
|
|
|
../verilog/syn.v
|
|
verilogSourceinclude
|
|
|
|
|
|
|
|
|
verilog
|
|
|
|
|
|
ipxact:library="Testbench"
|
|
ipxact:name="toolflow"
|
|
ipxact:version="verilog"/>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
common:*common:*
|
|
Verilog
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CPU_ADD16
|
sim:*Simulation:*
|
VEC_TABLE8'hff
|
Verilog
|
BOOT_ROM_WIDTH16
|
|
ROM_WRITETHRU0
|
fs-sim
|
|
|
|
|
|
|
|
syn:*Synthesis:*
|
|
Verilog
|
|
|
|
fs-sim
|
|
|
|
|
|
|
|
|
|
syn2:*Synthesis:*
|
|
Verilog
|
|
|
|
fs-syn
|
|
|
|
|
|
|
|
|
|
|
|
|
Hierarchical
|
|
|
|
|
|
spirit:library="Mos6502"
|
doc:*Documentation:*
|
spirit:name="T6502"
|
|
spirit:version="def.design"/>
|
|
|
ipxact:library="Testbench"
|
|
ipxact:name="toolflow"
|
|
ipxact:version="documentation"/>
|
|
|
|
|
|
Verilog
|
|
|
|
|
|
|
verilog
|
|
|
|
|
|
spirit:library="Testbench"
|
|
spirit:name="toolflow"
|
|
spirit:version="verilog"/>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
commoncommon
|
|
Verilog
|
|
|
|
|
|
|
|
|
|
sim:*Simulation:*
|
|
Verilog
|
|
|
|
fs-sim
|
|
|
|
|
|
|
|
syn:*Synthesis:*
|
|
Verilog
|
|
|
|
fs-sim
|
|
|
|
|
|
|
|
|
ext_addr
|
|
wire
|
|
out231
|
|
|
|
|
|
|
syn2:*Synthesis:*
|
ext_wdata
|
Verilog
|
wire
|
|
out150
|
fs-syn
|
|
|
|
|
|
|
|
|
ext_rdata
|
|
wire
|
|
in150
|
|
|
|
|
|
|
|
|
|
ext_ub
|
|
wire
|
|
out
|
|
|
|
|
|
ext_wait
|
|
wire
|
|
in
|
|
|
|
|
|
ext_lb
|
doc
|
wire
|
|
out
|
|
|
spirit:library="Testbench"
|
|
spirit:name="toolflow"
|
|
spirit:version="documentation"/>
|
|
|
|
:*Documentation:*
|
|
Verilog
|
|
|
|
|
|
|
ext_rd
|
|
wire
|
|
out
|
|
|
|
|
|
ext_stb
|
|
wire
|
|
out
|
|
|
|
|
|
ext_wr
|
|
wire
|
|
out
|
|
|
|
|
|
ext_cs
|
|
wire
|
|
out10
|
|
|
|
|
|
|
|
alu_status
|
|
wire
|
|
out70
|
|
|
|
|
|
cts_pad_in
|
|
wire
|
|
in
|
|
|
|
|
|
rts_pad_out
|
|
wire
|
|
out
|
|
|
|
|
|
|
ext_addr
|
|
wire
|
|
out231
|
|
|
|
|
|
|
gpio_0_out
|
ext_wdata
|
wire
|
wire
|
out70
|
out150
|
|
|
|
|
|
|
gpio_0_oe
|
ext_rdata
|
wire
|
wire
|
out70
|
in150
|
|
|
|
|
|
|
|
|
gpio_0_in
|
ext_ub
|
wire
|
wire
|
in70
|
out
|
|
|
|
|
|
ext_wait
|
gpio_1_out
|
wire
|
wire
|
in
|
out70
|
|
|
|
|
ext_lb
|
gpio_1_oe
|
wire
|
wire
|
out
|
out70
|
|
|
|
|
ext_rd
|
|
wire
|
|
out
|
|
|
|
|
|
ext_stb
|
gpio_1_in
|
wire
|
wire
|
out
|
in70
|
|
|
|
|
ext_wr
|
ext_irq_in
|
wire
|
wire
|
out
|
in30
|
|
|
|
|
ext_cs
|
|
wire
|
|
out10
|
|
|
|
|
|
|
|
alu_status
|
|
wire
|
|
out70
|
|
|
|
|
|
cts_pad_in
|
jsp_data_out
|
wire
|
wire
|
in
|
out70
|
|
|
|
|
rts_pad_out
|
|
wire
|
|
out
|
|
|
|
|
|
|
|
gpio_0_out
|
wb_jsp_dat_i
|
wire
|
wire
|
out70
|
in70
|
|
|
|
|
gpio_0_oe
|
|
wire
|
|
out70
|
|
|
|
|
|
|
biu_wr_strobe
|
|
wire
|
|
out
|
|
|
|
|
gpio_0_in
|
|
wire
|
|
in70
|
|
|
|
|
|
gpio_1_out
|
wb_jsp_stb_i
|
wire
|
wire
|
out70
|
in
|
|
|
|
|
gpio_1_oe
|
|
wire
|
|
out70
|
|
|
|
|
|
|
|
gpio_1_in
|
|
wire
|
|
in70
|
|
|
|
|
|
ext_irq_in
|
|
wire
|
|
in30
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
jsp_data_out
|
|
wire
|
|
out70
|
|
|
|
|
|
|
|
|
|
wb_jsp_dat_i
|
|
wire
|
|
in70
|
|
|
|
|
|
|
|
biu_wr_strobe
|
|
wire
|
fs-sim
|
out
|
|
|
|
|
|
|
|
|
|
|
../verilog/copyright.v
|
|
verilogSourceinclude
|
|
|
|
|
wb_jsp_stb_i
|
|
wire
|
|
in
|
../verilog/common/T6502_def
|
|
verilogSourcemodule
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
fs-syn
|
|
|
|
|
|
|
|
../verilog/syn.v
|
|
verilogSourceinclude
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
