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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [core/] [rtl/] [xml/] [core_def.xml] - Diff between revs 134 and 135

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Rev 134	Rev 135
Line 25...	Line 25...
`// You should have received a copy of the GNU Lesser General //`	`// You should have received a copy of the GNU Lesser General //`
`// Public License along with this source; if not, download it //`	`// Public License along with this source; if not, download it //`
`// from http://www.opencores.org/lgpl.shtml //`	`// from http://www.opencores.org/lgpl.shtml //`
`// //`	`// //`
`-->`	`-->`

`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`	`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
`xmlns:socgen="http://opencores.org"`	`xmlns:socgen="http://opencores.org"`
`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`	`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`	`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`

`opencores.org`	`opencores.org`
`Mos6502`	`Mos6502`
`core`	`core`
`def default`	`def`



`slave_clk`	`slave_clk`





`clk`
`clk`	`clk`
	`clk`








`slave_reset`	`slave_reset`





`reset`
`reset`	`reset`
	`reset`











`cpu`





`addr`
`addr`
`150`



`rdata`
`rdata`
`150`



`wdata`
`wdata`
`70`



`rd`
`rd`



`wr`
`wr`





	`cpu`






	`addr`
	`addr`
	`150`



	`rdata`
	`rdata`
	`150`



	`wdata`
	`wdata`
	`70`



	`rd`
	`rd`



	`wr`
	`wr`














`gen_verilog_sim`	`gen_verilog_sim`
`104.0`	`104.0`
`none`	`none`
`:Simulation:`	`:Simulation:`
`./tools/verilog/gen_verilog`	`tools/verilog/gen_verilog`


`destination`	`destination`
`core_def`	`core_def`





`gen_verilog_syn`	`gen_verilog_syn`
`104.0`	`104.0`
`none`	`none`
`:Synthesis:`	`:Synthesis:`
`./tools/verilog/gen_verilog`	`tools/verilog/gen_verilog`


`destination`	`destination`
`core_def`	`core_def`

















`fs-sim`	`fs-sim`



`../verilog/copyright.v`	`../verilog/copyright.v`
`verilogSourceinclude`	`verilogSourceinclude`




`../verilog/sim/core_def`	`../verilog/sim/core_def`
`verilogSourcemodule`	`verilogSourcemodule`






`../verilog/defines`	`../verilog/defines`
`verilogSourceinclude`	`verilogSourceinclude`




`alu`	`alu`
`../verilog/alu`	`../verilog/alu`
`verilogSourcemodule`	`verilogSourcemodule`



`alu_logic`	`alu_logic`
`../verilog/alu_logic`	`../verilog/alu_logic`
`verilogSourcemodule`	`verilogSourcemodule`




`control`	`control`
`../verilog/control`	`../verilog/control`
`verilogSourcemodule`	`verilogSourcemodule`




`inst_decode`	`inst_decode`
`../verilog/inst_decode`	`../verilog/inst_decode`
`verilogSourcemodule`	`verilogSourcemodule`



`sequencer`	`sequencer`
`../verilog/sequencer`	`../verilog/sequencer`
`verilogSourcemodule`	`verilogSourcemodule`





`state_fsm`	`state_fsm`
`../verilog/state_fsm`	`../verilog/state_fsm`
`verilogSourcemodule`	`verilogSourcemodule`





`../verilog/top.sim`	`../verilog/top.sim`
`verilogSourcefragment`	`verilogSourcefragment`




`../verilog/top.body`	`../verilog/top.body`
`verilogSourcefragment`	`verilogSourcefragment`










`fs-syn`	`fs-syn`



`../verilog/copyright.v`	`../verilog/copyright.v`
`verilogSourceinclude`	`verilogSourceinclude`





`../verilog/syn/core_def`	`../verilog/syn/core_def`
`verilogSourcemodule`	`verilogSourcemodule`




`../verilog/defines`	`../verilog/defines`
`verilogSourceinclude`	`verilogSourceinclude`




`alu`	`alu`
`../verilog/alu`	`../verilog/alu`
`verilogSourcemodule`	`verilogSourcemodule`



`alu_logic`	`alu_logic`
`../verilog/alu_logic`	`../verilog/alu_logic`
`verilogSourcemodule`	`verilogSourcemodule`




`control`	`control`
`../verilog/control`	`../verilog/control`
`verilogSourcemodule`	`verilogSourcemodule`




`inst_decode`	`inst_decode`
`../verilog/inst_decode`	`../verilog/inst_decode`
`verilogSourcemodule`	`verilogSourcemodule`



`sequencer`	`sequencer`
`../verilog/sequencer`	`../verilog/sequencer`
`verilogSourcemodule`	`verilogSourcemodule`





`state_fsm`	`state_fsm`
`../verilog/state_fsm`	`../verilog/state_fsm`
`verilogSourcemodule`	`verilogSourcemodule`






`../verilog/top.body`	`../verilog/top.body`
`verilogSourcefragment`	`verilogSourcefragment`



















`verilog`	`verilog`


`spirit:library="Testbench"`	`ipxact:library="Testbench"`
`spirit:name="toolflow"`	`ipxact:name="toolflow"`
`spirit:version="verilog"/>`	`ipxact:version="verilog"/>`








`sim:Simulation:`	`sim:Simulation:`
`Verilog`	`Verilog`
`fs-sim`	`fs-sim`



`syn:Synthesis:`	`syn:Synthesis:`
`Verilog`	`Verilog`
`fs-syn`	`fs-syn`




`doc`	`doc`


`spirit:library="Testbench"`	`ipxact:library="Testbench"`
`spirit:name="toolflow"`	`ipxact:name="toolflow"`
`spirit:version="documentation"/>`	`ipxact:version="documentation"/>`

`:Documentation:`	`:Documentation:`
`Verilog`	`Verilog`










`VEC_TABLE8'hff`
`BOOT_VEC8'hfc`








	`clk`
	`wire`
	`in`


`enable`	`reset`
`wire`	`wire`
`in`	`in`


	`enable`
	`wire`
	`in`



`nmi`	`addr`
`wire`	`wire`
`in`	`out`


`vec_int`
`wire`
`in`
`70`


	`wdata`
	`wire`
	`out`


`prog_data`
`wire`
`in`
`150`


	`rdata`
	`wire`
	`in`


`pg0_data`
`wire`
`in`
`70`


`alu_status`
`wire`
`out`
`70`


`prog_counter`	`rd`
`wire`	`wire`
`out`	`out`
`150`


`pg0_add`	`wr`
`wire`	`wire`
`out`	`out`
`70`


`pg0_rd`
`wire`
`out`


`pg0_wr`	`nmi`
`wire`	`wire`
`out`	`in`


	`vec_int`
	`wire`
	`in`
	`70`


`stk_push`
`wire`
`out`


`stk_push_data`	`prog_data`
`wire`	`wire`
`out`	`in`
`150`	`150`


`stk_pull`
`wire`
`out`


`stk_pull_data`	`pg0_data`
`wire`	`wire`
`in`	`in`
`150`	`70`


	`alu_status`
	`wire`
	`out`
	`70`


	`prog_counter`
	`wire`
	`out`
	`150`


	`pg0_add`
	`wire`
	`out`
	`70`


	`pg0_rd`
	`wire`
	`out`


	`pg0_wr`
	`wire`
	`out`



	`stk_push`
	`wire`
	`out`


	`stk_push_data`
	`wire`
	`out`
	`150`


	`stk_pull`
	`wire`
	`out`


	`stk_pull_data`
	`wire`
	`in`
	`150`

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [core/] [rtl/] [xml/] [core_def.xml] - Diff between revs 134 and 135