URL
https://opencores.org/ocsvn/socgen/socgen/trunk
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// Generated File Do Not EDIT //
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// Generated File Do Not EDIT //
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// //
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// //
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// regen by adding -tb to gen_verilog script //
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// regen by adding -tb to gen_verilog script //
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// //
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// //
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-->
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-->
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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
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xmlns:socgen="http://opencores.org"
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xmlns:socgen="http://opencores.org"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
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xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
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http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
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http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
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opencores.org
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opencores.org
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Mos6502
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Mos6502
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cpu
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cpu
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def.design
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def.design
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addr
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addr
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wire
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wire
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CPU_ADD-10
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CPU_ADD-10
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prog_counter
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prog_counter
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wire
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wire
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CPU_ADD-10
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CPU_ADD-10
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alu_status
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alu_status
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clk
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clk
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reset
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reset
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enable
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enable
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addr
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addr
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addr
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addr
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prog_counter
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prog_counter
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prog_data
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prog_data
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rd
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rd
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rdata
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rdata
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wdata
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wdata
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wr
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wr
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nmi
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nmi
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pg0_add
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pg0_add
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pg0_data
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pg0_data
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pg0_rd
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pg0_rd
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pg0_wr
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pg0_wr
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prog_counter
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prog_counter
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prog_data
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prog_data
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vec_int
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vec_int
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stk_push
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stk_push
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stk_push_data
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stk_push_data
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stk_pull
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stk_pull
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stk_pull_data
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stk_pull_data
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core
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core
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VEC_TABLE
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VEC_TABLE
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BOOT_VEC
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BOOT_VEC
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stack_ram
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stack_ram
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STACK_RAM_WIDTH
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STACK_RAM_WIDTH
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STACK_RAM_SIZE
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STACK_RAM_SIZE
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STACK_RAM_WORDS
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STACK_RAM_WORDS
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prog_rom
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prog_rom
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PROG_ROM_WIDTH
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PROG_ROM_WIDTH
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PROG_ROM_ADD
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PROG_ROM_ADD
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PROG_ROM_WORDS
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PROG_ROM_WORDS
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