URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [rtl/] [verilog/] [adbg_jfifo_module.v] - Diff between revs 131 and 135

Rev 131	Rev 135
Line 310...	Line 310...
`reg [2:0] wr_module_next_state; // combinatorial signal, not actually a register`	`reg [2:0] wr_module_next_state; // combinatorial signal, not actually a register`




`ifndef SYNTHESYS	`ifndef SYNTHESIS

`reg [8*16-1:0] wr_module_string;`	`reg [8*16-1:0] wr_module_string;`

`always @(*) begin`	`always @(*) begin`
`case (wr_module_state)`	`case (wr_module_state)`
Line 326...	Line 326...
`endcase`	`endcase`

`$display("%t %m JFifo wr_module State = %s",$realtime, wr_module_string);`	`$display("%t %m JFifo wr_module State = %s",$realtime, wr_module_string);`
`end`	`end`

`endif // `ifndef SYNTHESYS	`endif // `ifndef SYNTHESIS





Line 479...	Line 479...





`ifndef SYNTHESYS	`ifndef SYNTHESIS

`reg [8*16-1:0] rd_module_string;`	`reg [8*16-1:0] rd_module_string;`

`always @(*) begin`	`always @(*) begin`
`case (rd_module_state)`	`case (rd_module_state)`
Line 495...	Line 495...
`endcase`	`endcase`

`$display("%t %m JFifo rd_module State = %s",$realtime, rd_module_string);`	`$display("%t %m JFifo rd_module State = %s",$realtime, rd_module_string);`
`end`	`end`

`endif // `ifndef SYNTHESYS	`endif // `ifndef SYNTHESIS