OpenCores

Line 25...

//   You should have received a copy of the GNU Lesser General            //

//   You should have received a copy of the GNU Lesser General            //

//   Public License along with this source; if not, download it           //

//   Public License along with this source; if not, download it           //

//   from http://www.opencores.org/lgpl.shtml                             //

//   from http://www.opencores.org/lgpl.shtml                             //

//                                                                        //

//                                                                        //

-->

-->

xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"

xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"

xmlns:socgen="http://opencores.org"

xmlns:socgen="http://opencores.org"

xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"

xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"

xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009

xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014

http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">

http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">

opencores.org

opencores.org

adv_debug_sys

adv_debug_sys

adv_dbg_if

adv_dbg_if

wb_cpu0_jfifo  default

wb_cpu0_jfifo

  gen_verilog

  gen_verilog

  104.0

  104.0

  none

  none

  :*Simulation:*

  :*Simulation:*

  ./tools/verilog/gen_verilog

  tools/verilog/gen_verilog

      destination

      destination

      wb_cpu0_jfifo

      wb_cpu0_jfifo

      fs-sim

      fs-sim

        ../verilog/wb_cpu0_jfifo_defines.v

        ../verilog/wb_cpu0_jfifo_defines.v

        verilogSource

        verilogSource

        include

        include

        ../verilog/adbg_or1k_defines.v

        ../verilog/adbg_or1k_defines.v

        verilogSource

        verilogSource

        include

        include

        ../verilog/adbg_wb_defines.v

        ../verilog/adbg_wb_defines.v

        verilogSource

        verilogSource

        include

        include

        ../verilog/adbg_wb_cpu0_jfifo.v

        ../verilog/adbg_wb_cpu0_jfifo.v

        verilogSource

        verilogSource

        module

        module

        crc32

        crc32

        ../verilog/adbg_crc32.v

        ../verilog/adbg_crc32.v

        verilogSource

        verilogSource

        module

        module

        jfifo_biu

        jfifo_biu

        ../verilog/adbg_jfifo_biu.v

        ../verilog/adbg_jfifo_biu.v

        verilogSource

        verilogSource

        module

        module

        jfifo_module

        jfifo_module

        ../verilog/adbg_jfifo_module.v

        ../verilog/adbg_jfifo_module.v

        verilogSource

        verilogSource

        module

        module

        or1k_biu

        or1k_biu

        ../verilog/adbg_or1k_biu.v

        ../verilog/adbg_or1k_biu.v

        verilogSource

        verilogSource

        module

        module

        or1k_module

        or1k_module

        ../verilog/adbg_or1k_module.v

        ../verilog/adbg_or1k_module.v

        verilogSource

        verilogSource

        module

        module

        or1k_status_reg

        or1k_status_reg

        ../verilog/adbg_or1k_status_reg.v

        ../verilog/adbg_or1k_status_reg.v

        verilogSource

        verilogSource

        module

        module

        wb_biu

        wb_biu

        ../verilog/adbg_wb_biu.v

        ../verilog/adbg_wb_biu.v

        verilogSource

        verilogSource

        module

        module

        wb_module

        wb_module

        ../verilog/adbg_wb_module.v

        ../verilog/adbg_wb_module.v

        verilogSource

        verilogSource

        module

        module

        bytefifo

        bytefifo

        ../verilog/adbg_bytefifo.v

        ../verilog/adbg_bytefifo.v

        verilogSource

        verilogSource

        module

        module

        syncflop

        syncflop

        ../verilog/adbg_syncflop.v

        ../verilog/adbg_syncflop.v

        verilogSource

        verilogSource

        module

        module

        syncreg

        syncreg

        ../verilog/adbg_syncreg.v

        ../verilog/adbg_syncreg.v

        verilogSource

        verilogSource

        module

        module

      fs-syn

      fs-syn

        ../verilog/SYNTHESYS

        ../verilog/SYNTHESIS

        verilogSource

        verilogSource

        include

        include

        ../verilog/wb_cpu0_jfifo_defines.v

        ../verilog/wb_cpu0_jfifo_defines.v

        verilogSource

        verilogSource

        include

        include

        ../verilog/adbg_or1k_defines.v

        ../verilog/adbg_or1k_defines.v

        verilogSource

        verilogSource

        include

        include

        ../verilog/adbg_wb_defines.v

        ../verilog/adbg_wb_defines.v

        verilogSource

        verilogSource

        include

        include

        ../verilog/adbg_wb_cpu0_jfifo.v

        ../verilog/adbg_wb_cpu0_jfifo.v

        verilogSource

        verilogSource

        module

        module

        crc32

        crc32

        ../verilog/adbg_crc32.v

        ../verilog/adbg_crc32.v

        verilogSource

        verilogSource

        module

        module

        jfifo_biu

        jfifo_biu

        ../verilog/adbg_jfifo_biu.v

        ../verilog/adbg_jfifo_biu.v

        verilogSource

        verilogSource

        module

        module

        jfifo_module

        jfifo_module

        ../verilog/adbg_jfifo_module.v

        ../verilog/adbg_jfifo_module.v

        verilogSource

        verilogSource

        module

        module

        or1k_biu

        or1k_biu

        ../verilog/adbg_or1k_biu.v

        ../verilog/adbg_or1k_biu.v

        verilogSource

        verilogSource

        module

        module

        or1k_module

        or1k_module

        ../verilog/adbg_or1k_module.v

        ../verilog/adbg_or1k_module.v

        verilogSource

        verilogSource

        module

        module

        or1k_status_reg

        or1k_status_reg

        ../verilog/adbg_or1k_status_reg.v

        ../verilog/adbg_or1k_status_reg.v

        verilogSource

        verilogSource

        module

        module

        wb_biu

        wb_biu

        ../verilog/adbg_wb_biu.v

        ../verilog/adbg_wb_biu.v

        verilogSource

        verilogSource

        module

        module

        wb_module

        wb_module

        ../verilog/adbg_wb_module.v

        ../verilog/adbg_wb_module.v

        verilogSource

        verilogSource

        module

        module

        bytefifo

        bytefifo

        ../verilog/adbg_bytefifo.v

        ../verilog/adbg_bytefifo.v

        verilogSource

        verilogSource

        module

        module

        syncflop

        syncflop

        ../verilog/adbg_syncflop.v

        ../verilog/adbg_syncflop.v

        verilogSource

        verilogSource

        module

        module

        syncreg

        syncreg

        ../verilog/adbg_syncreg.v

        ../verilog/adbg_syncreg.v

        verilogSource

        verilogSource

        module

        module

              jtag

              jtag

                                   spirit:library="adv_debug_sys"

                                   ipxact:library="adv_debug_sys"

                                   spirit:name="adv_dbg_if"

                                   ipxact:name="adv_dbg_if"

                                   spirit:version="jtag_i"/>

                                   ipxact:version="jtag_i"/>

              cpu0

              cpu0

                                   spirit:library="adv_debug_sys"

                                   ipxact:library="adv_debug_sys"

                                   spirit:name="adv_dbg_if"

                                   ipxact:name="adv_dbg_if"

                                   spirit:version="cpu0_i"/>

                                   ipxact:version="cpu0_i"/>

wb

wb

                                   spirit:library="adv_debug_sys"

                                   ipxact:library="adv_debug_sys"

                                   spirit:name="adv_dbg_if"

                                   ipxact:name="adv_dbg_if"

                                   spirit:version="wb_i"/>

                                   ipxact:version="wb_i"/>

              jfifo

              jfifo

                                   spirit:library="adv_debug_sys"

                                   ipxact:library="adv_debug_sys"

                                   spirit:name="adv_dbg_if"

                                   ipxact:name="adv_dbg_if"

                                   spirit:version="jfifo_i"/>

                                   ipxact:version="jfifo_i"/>

              verilog

              verilog

                                   spirit:library="Testbench"

                                   ipxact:library="Testbench"

                                   spirit:name="toolflow"

                                   ipxact:name="toolflow"

                                   spirit:version="verilog"/>

                                   ipxact:version="verilog"/>

              sim:*Simulation:*

              sim:*Simulation:*

              Verilog

              Verilog

                            fs-sim

                            fs-sim

              syn:*Synthesis:*

              syn:*Synthesis:*

              Verilog

              Verilog

                            fs-syn

                            fs-syn

doc

doc

                                   spirit:library="Testbench"

                                   ipxact:library="Testbench"

                                   spirit:name="toolflow"

                                   ipxact:name="toolflow"

                                   spirit:version="documentation"/>

                                   ipxact:version="documentation"/>

              :*Documentation:*

              :*Documentation:*

              Verilog

              Verilog

int_o

int_o

wire

wire

out

out

biu_wr_strobe

biu_wr_strobe

wire

wire

out

out

jsp_data_out

jsp_data_out

reg

reg

out70

out70

Line 487...

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [rtl/] [xml/] [adv_dbg_if_wb_cpu0_jfifo.xml] - Diff between revs 134 and 135