| Line 25... |
Line 25... |
// You should have received a copy of the GNU Lesser General //
|
// You should have received a copy of the GNU Lesser General //
|
// Public License along with this source; if not, download it //
|
// Public License along with this source; if not, download it //
|
// from http://www.opencores.org/lgpl.shtml //
|
// from http://www.opencores.org/lgpl.shtml //
|
// //
|
// //
|
-->
|
-->
|
|
|
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
|
xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
|
xmlns:socgen="http://opencores.org"
|
xmlns:socgen="http://opencores.org"
|
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
|
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
|
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
|
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
|
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
|
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
|
opencores.org
|
opencores.org
|
fpgas
|
fpgas
|
Nexys2_T6502
|
Nexys2_T6502
|
default default
|
default
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
gen_verilog
|
gen_verilog
|
104.0
|
104.0
|
none
|
none
|
common
|
:*common:*
|
./tools/verilog/gen_verilog
|
tools/verilog/gen_verilog
|
|
|
|
|
destination
|
destination
|
Nexys2_T6502_default
|
Nexys2_T6502_default
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Hierarchical:*Simulation:*
|
|
|
|
spirit:library="fpgas"
|
|
spirit:name="Nexys2_T6502"
|
|
spirit:version="fpga.design"/>
|
|
|
|
|
|
|
|
Pad_Ring:*Simulation:*
|
|
|
Hierarchical
|
|
|
|
|
|
|
|
|
|
|
|
|
spirit:library="Nexys2"
|
|
spirit:name="fpga"
|
|
spirit:version="jtag_padring"/>
|
|
|
|
|
|
|
|
|
|
verilog:*Simulation:*
|
|
|
|
|
|
spirit:library="Testbench"
|
|
spirit:name="toolflow"
|
|
spirit:version="verilog"/>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Hierarchical:*Simulation:*
|
|
|
|
Hierarchical
|
commoncommon
|
|
Verilog
|
|
|
|
fs-common
|
|
|
|
|
|
|
|
|
|
|
|
|
Pad_Ring:*Simulation:*
|
|
|
|
|
sim:*Simulation:*
|
|
Verilog
|
ipxact:library="Nexys2"
|
|
ipxact:name="fpga"
|
fs-sim
|
ipxact:version="jtag_padring"/>
|
|
|
|
|
|
|
|
|
|
verilog:*Simulation:*
|
|
|
|
|
|
ipxact:library="Testbench"
|
|
ipxact:name="toolflow"
|
|
ipxact:version="verilog"/>
|
|
|
|
|
|
|
|
|
syn:*Synthesis:*
|
|
Verilog
|
|
|
|
fs-sim
|
|
|
|
|
|
|
|
|
|
|
common:*common:*
|
|
Verilog
|
|
|
|
fs-common
|
|
|
|
|
|
|
|
|
doc:*Simulation:*
|
|
|
|
|
|
spirit:library="Testbench"
|
|
spirit:name="toolflow"
|
|
spirit:version="documentation"/>
|
|
|
|
:*Documentation:*
|
|
Verilog
|
|
|
|
|
|
|
|
|
sim:*Simulation:*
|
|
Verilog
|
|
|
|
fs-sim
|
|
|
|
|
|
|
|
|
|
|
|
syn:*Synthesis:*
|
|
Verilog
|
|
|
|
fs-sim
|
|
|
|
|
|
|
|
|
|
|
|
|
|
doc:*Simulation:*
|
|
|
|
|
|
ipxact:library="Testbench"
|
|
ipxact:name="toolflow"
|
|
ipxact:version="documentation"/>
|
|
|
|
:*Documentation:*
|
|
Verilog
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
fs-sim
|
|
|
|
|
|
|
|
../verilog/copyright
|
|
verilogSourceinclude
|
|
|
|
|
|
|
|
|
|
../verilog/common/Nexys2_T6502_default
|
|
verilogSourcemodule
|
|
|
|
|
|
|
|
dest_dir
|
|
../views/sim/
|
|
verilogSourcelibraryDir
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
fs-sim
|
|
|
|
|
fs-syn
|
|
|
../verilog/copyright
|
|
verilogSourceinclude
|
|
|
|
|
|
|
|
|
../verilog/copyright
|
../verilog/common/Nexys2_T6502_default
|
verilogSourceinclude
|
verilogSourcemodule
|
|
|
|
|
|
|
|
dest_dir
|
../verilog/common/Nexys2_T6502_default
|
../views/sim/
|
verilogSourcemodule
|
verilogSourcelibraryDir
|
|
|
|
|
|
|
dest_dir
|
|
../views/syn/
|
|
verilogSourcelibraryDir
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
fs-syn
|
|
|
|
|
|
|
|
../verilog/copyright
|
|
verilogSourceinclude
|
|
|
|
|
|
|
fs-lint
|
|
|
../verilog/common/Nexys2_T6502_default
|
|
verilogSourcemodule
|
|
|
|
|
|
|
dest_dir
|
dest_dir
|
../views/syn/
|
../views/syn/
|
verilogSourcelibraryDir
|
verilogSourcelibraryDir
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
fs-lint
|
|
|
|
|
|
dest_dir
|
|
../views/syn/
|
|
verilogSourcelibraryDir
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
