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https://opencores.org/ocsvn/socgen/socgen/trunk
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// //
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// //
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// //
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// //
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// //
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// //
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// //
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// //
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-->
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-->
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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
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xmlns:socgen="http://opencores.org"
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xmlns:socgen="http://opencores.org"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
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xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
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http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
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http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
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opencores.org
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opencores.org
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fpgas
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fpgas
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Nexys2_T6502
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Nexys2_T6502
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default_dut.params
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default_dut.params
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Dut
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Dut
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spirit:library="fpgas"
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ipxact:library="fpgas"
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spirit:name="Nexys2_T6502"
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ipxact:name="Nexys2_T6502"
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spirit:version="default_duth.design"/>
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ipxact:version="default_duth.design"/>
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RAM_WORDS2048
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RAM_WORDS2048
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RAM_ADD11
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RAM_ADD11
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ROM_WORDS128
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ROM_WORDS128
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ROM_ADD7
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ROM_ADD7
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ROM_FILE"NONE"
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ROM_FILE"NONE"
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PROG_ROM_FILE"NONE"
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PROG_ROM_FILE"NONE"
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PROG_ROM_WORDS128
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PROG_ROM_WORDS128
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PROG_ROM_ADD7
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PROG_ROM_ADD7
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VEC_TABLE8'hff
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VEC_TABLE8'hff
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STARTUP"NONE"
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STARTUP"NONE"
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FONT"NONE"
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FONT"NONE"
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CLOCK_FREQ50
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CLOCK_FREQ50
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CLOCK_PLL_MULT2
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CLOCK_PLL_MULT2
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CLOCK_PLL_DIV4
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CLOCK_PLL_DIV4
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CLOCK_PLL_SIZE4
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CLOCK_PLL_SIZE4
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CLOCK_SRC0
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CLOCK_SRC0
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RESET_SENSE0
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RESET_SENSE0
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UART_PRESCALE5'b01100
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UART_PRESCALE5'b01100
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UART_PRE_SIZE5
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UART_PRE_SIZE5
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UART_DIV0
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UART_DIV0
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JTAG_USER1_WIDTH8
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JTAG_USER1_WIDTH8
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JTAG_USER1_RESET8'h12
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JTAG_USER1_RESET8'h12
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