URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [fpgas/] [ip/] [Nexys2_T6502/] [syn/] [chips/] [xml/] [Nexys2_T6502_chip.xml] - Diff between revs 134 and 135

Rev 134	Rev 135
Line 25...	Line 25...
`// You should have received a copy of the GNU Lesser General //`	`// You should have received a copy of the GNU Lesser General //`
`// Public License along with this source; if not, download it //`	`// Public License along with this source; if not, download it //`
`// from http://www.opencores.org/lgpl.shtml //`	`// from http://www.opencores.org/lgpl.shtml //`
`// //`	`// //`
`-->`	`-->`

`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`	`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
`xmlns:socgen="http://opencores.org"`	`xmlns:socgen="http://opencores.org"`
`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`	`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`	`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
`opencores.org`	`opencores.org`
`fpgas`	`fpgas`
`Nexys2_T6502`	`Nexys2_T6502`
`chip`	`chip`






`fs-syn`	`fs-syn`



`../verilog/copyright.v`	`../verilog/copyright.v`
`verilogSource`	`verilogSource`
`include`	`include`




`../verilog/sram.load`	`../verilog/sram.load`
`verilogSource`	`verilogSource`
`fragment`	`fragment`












`syn:Synthesis:`	`syn:Synthesis:`
`Verilog`	`Verilog`