| Line 25... |
Line 25... |
// You should have received a copy of the GNU Lesser General //
|
// You should have received a copy of the GNU Lesser General //
|
// Public License along with this source; if not, download it //
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// Public License along with this source; if not, download it //
|
// from http://www.opencores.org/lgpl.shtml //
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// from http://www.opencores.org/lgpl.shtml //
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// //
|
// //
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-->
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-->
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|
|
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
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xmlns:socgen="http://opencores.org"
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xmlns:socgen="http://opencores.org"
|
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
|
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
|
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
|
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
|
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
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|
|
opencores.org
|
opencores.org
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io
|
io
|
io_ext_mem_interface
|
io_ext_mem_interface
|
def default
|
def
|
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slave_clk
|
slave_clk
|
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clk
|
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clk
|
clk
|
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clk
|
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slave_reset
|
slave_reset
|
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reset
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reset
|
reset
|
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reset
|
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mb
|
mb
|
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little
|
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8
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rdata
|
rdata
|
|
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rdata
|
rdata
|
wire
|
70
|
70
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|
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addr
|
addr
|
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addr
|
addr
|
30
|
30
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|
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wdata
|
wdata
|
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wdata
|
wdata
|
70
|
70
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rd
|
rd
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rd
|
rd
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wr
|
wr
|
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wr
|
wr
|
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cs
|
cs
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cs
|
cs
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little
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8
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mem
|
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addr
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mem_addr
|
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130
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cs
|
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mem_cs
|
|
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|
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|
|
|
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rdata
|
|
|
|
mem_rdata
|
|
150
|
|
|
|
|
|
|
|
|
|
|
|
|
mem
|
wdata
|
|
|
|
mem_wdata
|
|
150
|
|
|
|
|
|
|
|
|
|
|
addr
|
|
|
|
mem_addr
|
|
130
|
|
|
|
|
|
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|
rd
|
cs
|
|
|
mem_rd
|
mem_cs
|
|
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wr
|
|
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mem_wr
|
|
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|
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|
|
|
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rdata
|
|
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|
mem_rdata
|
|
150
|
|
|
|
|
|
|
|
|
wait
|
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|
mem_wait
|
|
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|
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|
|
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|
wdata
|
|
|
|
mem_wdata
|
|
150
|
|
|
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|
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|
rd
|
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mem_rd
|
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wr
|
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mem_wr
|
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wait
|
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mem_wait
|
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ext
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addr
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ext_add
|
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reg
|
|
231
|
|
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wdata
|
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ext_wdata
|
|
reg
|
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150
|
|
|
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|
|
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rdata
|
|
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|
ext_rdata
|
|
wire
|
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150
|
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rd
|
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ext_rd
|
|
reg
|
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wr
|
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ext_wr
|
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reg
|
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wait
|
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ext_wait
|
|
wire
|
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|
cs
|
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ext_cs
|
|
reg
|
|
10
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ext
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addr
|
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ext_add
|
|
reg
|
|
231
|
|
|
|
|
|
|
|
|
|
|
|
wdata
|
|
|
|
ext_wdata
|
|
reg
|
|
150
|
|
|
|
|
|
|
|
|
|
|
|
rdata
|
|
|
|
ext_rdata
|
|
wire
|
|
150
|
|
|
|
|
|
|
|
|
|
|
|
rd
|
|
|
|
ext_rd
|
|
reg
|
|
|
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|
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|
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|
wr
|
|
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|
ext_wr
|
|
reg
|
|
|
|
|
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|
|
|
|
|
|
wait
|
|
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|
ext_wait
|
|
wire
|
|
|
|
|
|
|
|
|
|
|
gen_registers
|
cs
|
102.1
|
|
common
|
ext_cs
|
none
|
reg
|
./tools/regtool/gen_registers
|
10
|
|
|
|
|
bus_intf
|
|
mb
|
|
|
|
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|
dest_dir
|
|
../verilog
|
|
|
|
|
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|
|
|
|
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|
gen_verilog
|
|
104.0
|
|
none
|
|
common
|
|
./tools/verilog/gen_verilog
|
|
|
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|
destination
|
|
io_ext_mem_interface_def
|
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|
fs-common
|
|
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|
../verilog/top.body
|
|
verilogSourcefragment
|
|
|
|
|
|
|
|
|
|
|
|
fs-sim
|
|
|
|
|
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|
|
../verilog/copyright.v
|
|
verilogSourceinclude
|
|
|
|
|
|
|
|
../verilog/common/io_ext_mem_interface_def
|
|
verilogSourcemodule
|
|
|
|
|
|
|
|
|
|
mb
|
|
../verilog/io_ext_mem_interface_def_mb
|
|
verilogSourcemodule
|
|
|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
fs-syn
|
gen_registers
|
|
102.1
|
|
:*common:*
|
|
none
|
|
tools/regtool/gen_registers
|
|
|
|
|
|
bus_intf
|
|
mb
|
|
|
|
|
|
dest_dir
|
|
../verilog
|
|
|
|
|
|
|
|
|
|
|
|
gen_verilog
|
../verilog/copyright.v
|
104.0
|
verilogSourceinclude
|
none
|
|
:*common:*
|
|
tools/verilog/gen_verilog
|
|
|
|
|
|
destination
|
|
io_ext_mem_interface_def
|
|
|
|
|
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|
../verilog/common/io_ext_mem_interface_def
|
|
verilogSourcemodule
|
|
|
|
|
|
|
|
|
|
mb
|
|
../verilog/io_ext_mem_interface_def_mb
|
|
verilogSourcemodule
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
fs-common
|
|
|
|
|
|
|
|
../verilog/top.body
|
|
verilogSourcefragment
|
|
|
|
|
|
|
|
|
|
|
|
fs-sim
|
|
|
|
|
|
|
|
../verilog/copyright.v
|
|
verilogSourceinclude
|
|
|
|
|
|
|
|
../verilog/common/io_ext_mem_interface_def
|
|
verilogSourcemodule
|
|
|
|
|
|
|
|
|
|
mb
|
|
../verilog/io_ext_mem_interface_def_mb
|
|
verilogSourcemodule
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Hierarchical
|
|
|
|
|
|
spirit:library="io"
|
|
spirit:name="io_ext_mem_interface"
|
|
spirit:version="def.design"/>
|
|
|
|
|
|
|
|
|
|
verilog
|
fs-syn
|
|
|
|
|
spirit:library="Testbench"
|
|
spirit:name="toolflow"
|
|
spirit:version="verilog"/>
|
|
|
|
|
|
|
|
|
|
|
|
|
../verilog/copyright.v
|
|
verilogSourceinclude
|
|
|
|
|
|
|
|
|
|
../verilog/common/io_ext_mem_interface_def
|
|
verilogSourcemodule
|
|
|
|
|
|
|
|
|
|
mb
|
|
../verilog/io_ext_mem_interface_def_mb
|
|
verilogSourcemodule
|
|
|
|
|
|
|
commoncommon
|
|
|
|
Verilog
|
|
|
|
|
|
fs-common
|
|
|
|
|
|
|
|
|
|
sim:*Simulation:*
|
|
|
|
Verilog
|
|
|
|
|
|
fs-sim
|
|
|
|
|
|
|
|
|
|
|
|
syn:*Synthesis:*
|
|
|
|
Verilog
|
|
|
|
|
|
fs-syn
|
|
|
|
|
|
|
|
|
|
|
|
|
|
doc
|
|
|
|
|
|
spirit:library="Testbench"
|
|
spirit:name="toolflow"
|
|
spirit:version="documentation"/>
|
|
|
|
:*Documentation:*
|
|
Verilog
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Hierarchical
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
enable
|
|
wire
|
Hierarchical
|
in
|
Hierarchical
|
|
|
|
|
|
|
|
|
|
verilog
|
|
|
|
|
|
ipxact:library="Testbench"
|
|
ipxact:name="toolflow"
|
|
ipxact:version="verilog"/>
|
|
|
|
|
|
|
|
|
wait_st
|
|
wire
|
|
out
|
|
70
|
|
|
|
|
|
|
|
|
|
|
|
|
common:*common:*
|
|
|
|
Verilog
|
|
|
|
|
|
fs-common
|
|
|
|
|
|
|
|
|
|
sim:*Simulation:*
|
|
|
bank
|
Verilog
|
wire
|
|
out
|
|
70
|
fs-sim
|
|
|
|
|
|
|
|
|
|
|
|
syn:*Synthesis:*
|
|
|
|
Verilog
|
|
|
|
|
|
fs-syn
|
|
|
|
|
|
|
|
|
|
|
|
|
|
doc
|
|
|
|
|
|
ipxact:library="Testbench"
|
|
ipxact:name="toolflow"
|
|
ipxact:version="documentation"/>
|
|
|
|
:*Documentation:*
|
|
Verilog
|
|
|
|
|
ext_ub
|
|
reg
|
|
out
|
|
|
|
|
|
ext_stb
|
|
reg
|
|
out
|
|
|
|
|
|
|
|
|
|
|
|
ext_lb
|
|
reg
|
|
out
|
|
|
|
|
|
|
|
|
|
|
|
|
enable
|
|
wire
|
|
in
|
|
|
|
|
|
|
|
|
|
clk
|
|
wire
|
|
in
|
|
|
|
|
|
|
|
reset
|
|
wire
|
|
in
|
|
|
|
|
|
|
|
cs
|
|
wire
|
|
in
|
|
|
|
|
|
|
|
|
|
rd
|
mb
|
wire
|
8
|
in
|
|
|
mb
|
|
0x0
|
|
|
|
ext_mem
|
|
0x10
|
|
8
|
|
|
|
bank
|
|
0x2
|
|
8
|
|
read-write
|
|
|
|
|
|
wait_st
|
|
0x0
|
|
8
|
|
read-write
|
|
|
|
|
|
|
|
|
|
|
|
|
wr
|
|
wire
|
|
in
|
|
|
|
|
|
|
|
addr
|
mem
|
wire
|
8
|
in
|
|
30
|
mem
|
|
0x0
|
|
|
|
mem
|
|
0x4000
|
|
16
|
|
|
|
|
|
|
|
|
|
|
|
|
wdata
|
|
wire
|
|
in
|
|
70
|
|
|
|
|
|
|
|
rdata
|
|
wire
|
|
out
|
|
70
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
wait_st
|
|
wire
|
|
out
|
|
70
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
bank
|
|
wire
|
|
out
|
|
70
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
mem_cs
|
|
wire
|
|
in
|
|
|
|
|
|
|
|
mem_rd
|
|
wire
|
|
in
|
|
|
|
|
|
mem_wr
|
|
wire
|
|
in
|
|
|
|
|
|
|
|
mem_addr
|
|
wire
|
|
in
|
|
130
|
|
|
|
|
|
|
|
mem_wdata
|
|
wire
|
|
in
|
|
150
|
|
|
|
|
|
|
|
mem_rdata
|
|
wire
|
|
out
|
|
150
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
ext_cs
|
|
wire
|
|
out
|
|
|
|
|
|
|
|
ext_rd
|
|
wire
|
|
out
|
|
|
|
|
|
ext_wr
|
|
wire
|
|
out
|
|
|
|
|
|
|
|
ext_addr
|
|
wire
|
|
out
|
|
230
|
|
|
|
|
|
|
|
ext_wdata
|
|
wire
|
|
out
|
|
150
|
|
|
|
|
|
|
|
ext_rdata
|
|
wire
|
|
in
|
|
150
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
ext_ub
|
|
reg
|
|
out
|
|
|
|
|
|
ext_stb
|
|
reg
|
|
out
|
|
|
|
|
|
|
|
|
|
ext_lb
|
|
reg
|
|
out
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
mb
|
|
8
|
|
|
|
mb
|
|
0x0
|
|
|
|
ext_mem
|
|
0x10
|
|
8
|
|
|
|
bank
|
|
0x2
|
|
8
|
|
read-write
|
|
|
|
|
|
wait_st
|
|
0x0
|
|
8
|
|
read-write
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
mem
|
|
8
|
|
|
|
mem
|
|
0x0
|
|
|
|
mem
|
|
0x4000
|
|
16
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
