URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_module/] [rtl/] [xml/] [io_module_def.xml] - Diff between revs 134 and 135

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Rev 134	Rev 135
Line 25...	Line 25...
`// You should have received a copy of the GNU Lesser General //`	`// You should have received a copy of the GNU Lesser General //`
`// Public License along with this source; if not, download it //`	`// Public License along with this source; if not, download it //`
`// from http://www.opencores.org/lgpl.shtml //`	`// from http://www.opencores.org/lgpl.shtml //`
`// //`	`// //`
`-->`	`-->`

`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`	`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
`xmlns:socgen="http://opencores.org"`	`xmlns:socgen="http://opencores.org"`
`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`	`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`	`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`

`opencores.org`	`opencores.org`
`io`	`io`
`io_module`	`io_module`
`def default`	`def`



`slave_clk`	`slave_clk`





`clk`
`clk`	`clk`
	`clk`








`slave_reset`	`slave_reset`





`reset`
`reset`	`reset`
	`reset`








`slave_enable`	`slave_enable`





`enable`
`enable`	`enable`
	`enable`
















`gen_registers`	`gen_registers`
`102.1`	`102.1`
`common`	`:common:`
`none`	`none`
`./tools/regtool/gen_registers`	`tools/regtool/gen_registers`


`bus_intf`	`bus_intf`
`mb`	`mb`


`dest_dir`	`dest_dir`
`../verilog`	`../verilog`







`gen_verilog`	`gen_verilog`
`104.0`	`104.0`
`none`	`none`
`common`	`:common:`
`./tools/verilog/gen_verilog`	`tools/verilog/gen_verilog`


`destination`	`destination`
`io_module_def`	`io_module_def`












`fs-common`	`fs-common`



`../verilog/top.rtl`	`../verilog/top.rtl`
`verilogSourcefragment`	`verilogSourcefragment`






`fs-sim`	`fs-sim`



`../verilog/copyright`	`../verilog/copyright`
`verilogSourceinclude`	`verilogSourceinclude`




`../verilog/common/io_module_def`	`../verilog/common/io_module_def`
`verilogSourcemodule`	`verilogSourcemodule`





`dest_dir`	`dest_dir`
`../views/sim/`	`../views/sim/`
`verilogSourcelibraryDir`	`verilogSourcelibraryDir`







`fs-syn`	`fs-syn`




`../verilog/copyright`	`../verilog/copyright`
`verilogSourceinclude`	`verilogSourceinclude`




`../verilog/common/io_module_def`	`../verilog/common/io_module_def`
`verilogSourcemodule`	`verilogSourcemodule`




`dest_dir`	`dest_dir`
`../views/syn/`	`../views/syn/`
`verilogSourcelibraryDir`	`verilogSourcelibraryDir`



















	`Hierarchical`





`Hierarchical`


`spirit:library="io"`
`spirit:name="io_module"`
`spirit:version="def.design"/>`



`verilog`


`spirit:library="Testbench"`
`spirit:name="toolflow"`
`spirit:version="verilog"/>`






	`Hierarchical`
	`Hierarchical`




	`verilog`


	`ipxact:library="Testbench"`
	`ipxact:name="toolflow"`
	`ipxact:version="verilog"/>`




`commoncommon`
`Verilog`


`fs-common`




`sim:Simulation:`
`Verilog`


`fs-sim`





`syn:Synthesis:`
`Verilog`


`fs-syn`




	`common:common:`
	`Verilog`


	`fs-common`




	`sim:Simulation:`
	`Verilog`


	`fs-sim`





`doc`	`syn:Synthesis:`
	`Verilog`

`spirit:library="Testbench"`
`spirit:name="toolflow"`	`fs-syn`
`spirit:version="documentation"/>`

`:Documentation:`
`Verilog`







	`doc`


	`ipxact:library="Testbench"`
	`ipxact:name="toolflow"`
	`ipxact:version="documentation"/>`

	`:Documentation:`
	`Verilog`









`gpio_0_out`
`wire`
`out`
`70`


`gpio_0_oe`
`wire`
`out`
`70`



	`clk`
	`wire`
	`in`


`gpio_0_in`
`wire`
`in`
`70`


`gpio_1_out`	`reset`
`wire`	`wire`
`out`	`in`
`70`


`gpio_1_oe`
`wire`
`out`
`70`


	`enable`
	`wire`
	`in`



`gpio_1_in`
`wire`
`in`
`70`


`timer_irq`	`gpio_0_out`
`wire`	`wire`
`out`	`out`
`10`	`70`


`pic_irq`	`gpio_0_oe`
`wire`	`wire`
`out`	`out`
	`70`


`pic_nmi`
`wire`
`out`


`pic_irq_in`
`wire`
`in`
`70`


`vic_irq_in`	`gpio_0_in`
`wire`	`wire`
`in`	`in`
`70`	`70`


	`gpio_1_out`
	`wire`
	`out`
	`70`


`cts_pad_in`	`gpio_1_oe`
`wire`	`wire`
`in`	`out`
	`70`


`rts_pad_out`
`wire`
`out`


`rx_irq`
`wire`
`out`


`tx_irq`	`gpio_1_in`
`wire`	`wire`
`out`	`in`
	`70`


`ps2_data_avail`	`timer_irq`
`wire`	`wire`
`out`	`out`
	`10`


`y_pos`	`pic_irq`
`wire`	`wire`
`out`	`out`
`90`


`x_pos`	`pic_nmi`
`wire`	`wire`
`out`	`out`
`90`


`new_packet`	`pic_irq_in`
`wire`	`wire`
`out`	`in`
	`70`


`ms_mid`	`vic_irq_in`
`wire`	`wire`
`out`	`in`
	`70`


`ms_right`
`wire`
`out`


`ms_left`	`cts_pad_in`
`wire`	`wire`
`out`	`in`


`int_out`	`rts_pad_out`
`wire`	`wire`
`out`	`out`


`vector`	`rx_irq`
`wire`	`wire`
`out`	`out`
`70`


	`tx_irq`
	`wire`
	`out`


	`ps2_data_avail`
	`wire`
	`out`


	`y_pos`
	`wire`
	`out`
	`90`


`ext_ub`	`x_pos`
`wire`	`wire`
`out`	`out`
	`90`


`ext_stb`	`new_packet`
`wire`	`wire`
`out`	`out`


	`ms_mid`
	`wire`
	`out`


`ext_lb`	`ms_right`
`wire`	`wire`
`out`	`out`


	`ms_left`
	`wire`
	`out`


	`int_out`
	`wire`
	`out`


	`vector`
	`wire`
	`out`
	`70`






	`ext_ub`
	`wire`
	`out`


	`ext_stb`
	`wire`
	`out`




	`ext_lb`
	`wire`
	`out`




`8`
`mb`


`mb`
`0x00`


`gpio`
`0x10`
`8`




`0_out`
`0x02`
`8`
`read-write`



`0_oe`
`0x01`
`8`
`read-write`



`0_in`
`0x00`
`8`
`read-only`





`1_out`
`0x06`
`8`
`read-write`



`1_oe`
`0x05`
`8`
`read-write`



`1_in`	`8`
`0x04`	`mb`
`8`
`read-only`



	`mb`
	`0x00`


	`gpio`
	`0x10`
	`8`



	`0_out`
	`0x02`
	`8`
	`read-write`



	`0_oe`
	`0x01`
	`8`
	`read-write`



	`0_in`
	`0x00`
	`8`
	`read-only`




	`1_out`
	`0x06`
	`8`
	`read-write`



	`1_oe`
	`0x05`
	`8`
	`read-write`



	`1_in`
	`0x04`
	`8`
	`read-only`




`gpio`	`gpio`
`mb`	`mb`







`timer`	`timer`
`0x10`	`0x10`
`8`	`8`


`0_start`	`0_start`
`0x00`	`0x00`
`8`	`8`
`read-only`	`read-only`



`0_count`	`0_count`
`0x02`	`0x02`
`8`	`8`
`read-only`	`read-only`



`0_end`	`0_end`
`0x04`	`0x04`
`8`	`8`
`write-only`	`write-only`




`1_start`	`1_start`
`0x08`	`0x08`
`8`	`8`
`read-only`	`read-only`



`1_count`	`1_count`
`0x0a`	`0x0a`
`8`	`8`
`read-only`	`read-only`



`1_end`	`1_end`
`0x0c`	`0x0c`
`8`	`8`
`write-only`	`write-only`





`timer`	`timer`
`mb`	`mb`






`uart`	`uart`
`0x10`	`0x10`
`8`	`8`


`xmit_data`	`xmit_data`
`0x00`	`0x00`
`8`	`8`
`write-only`	`write-only`



`rcv_data`	`rcv_data`
`0x02`	`0x02`
`8`	`8`
`read-only`	`read-only`




`cntrl`	`cntrl`
`0x04`	`0x04`
`8`	`8`
`read-write`	`read-write`



`status`	`status`
`0x06`	`0x06`
`8`	`8`
`read-only`	`read-only`





`uart`	`uart`
`mb`	`mb`








`pic`	`pic`
`0x10`	`0x10`
`8`	`8`


`int_in`	`int_in`
`0x00`	`0x00`
`8`	`8`
`read-only`	`read-only`



`irq_enable`	`irq_enable`
`0x02`	`0x02`
`8`	`8`
`read-write`	`read-write`



`nmi_enable`	`nmi_enable`
`0x04`	`0x04`
`8`	`8`
`read-write`	`read-write`




`irq_act`	`irq_act`
`0x06`	`0x06`
`8`	`8`
`read-only`	`read-only`



`nmi_act`	`nmi_act`
`0x08`	`0x08`
`8`	`8`
`read-only`	`read-only`







`pic`	`pic`
`mb`	`mb`








`ps2`	`ps2`
`0x10`	`0x10`
`8`	`8`



`data`	`data`
`0x00`	`0x00`
`8`	`8`
`read-only`	`read-only`




`wdata_buf`	`wdata_buf`
`0x00`	`0x00`
`8`	`8`
`write-only`	`write-only`




`status`	`status`
`0x02`	`0x02`
`8`	`8`
`read-only`	`read-only`



`cntrl`	`cntrl`
`0x04`	`0x04`
`8`	`8`
`read-write`	`read-write`




`x_pos`	`x_pos`
`0x06`	`0x06`
`8`	`8`
`read-only`	`read-only`



`y_pos`	`y_pos`
`0x08`	`0x08`
`8`	`8`
`read-only`	`read-only`



`ps2`	`ps2`
`mb`	`mb`







`utimer`	`utimer`
`0x10`	`0x10`
`8`	`8`


`latch`	`latch`
`0x00`	`0x00`
`8`	`8`
`read-write`	`read-write`



`count`	`count`
`0x02`	`0x02`
`8`	`8`
`read-write`	`read-write`




`utimer`	`utimer`
`mb`	`mb`








`vga`	`vga`
`0x10`	`0x10`
`8`	`8`


`ascii_data`	`ascii_data`
`0x00`	`0x00`
`8`	`8`
`write-only`	`write-only`



`add_l`	`add_l`
`0x02`	`0x02`
`8`	`8`
`write-only`	`write-only`



`add_h`	`add_h`
`0x04`	`0x04`
`8`	`8`
`write-only`	`write-only`




`vadd_l`	`vadd_l`
`0x02`	`0x02`
`8`	`8`
`read-only`	`read-only`



`vadd_h`	`vadd_h`
`0x04`	`0x04`
`8`	`8`
`read-only`	`read-only`




`cntrl`	`cntrl`
`0x06`	`0x06`
`8`	`8`
`read-write`	`read-write`






`char_color`	`char_color`
`0x08`	`0x08`
`8`	`8`
`read-write`	`read-write`





`back_color`	`back_color`
`0x0a`	`0x0a`
`8`	`8`
`read-write`	`read-write`




`cursor_color`	`cursor_color`
`0x0c`	`0x0c`
`8`	`8`
`read-write`	`read-write`



`vga`	`vga`
`mb`	`mb`








`ext_mem`	`ext_mem`
`0x10`	`0x10`
`8`	`8`



`bank`	`bank`
`0x02`	`0x02`
`8`	`8`
`read-write`	`read-write`



`wait_st`	`wait_st`
`0x00`	`0x00`
`8`	`8`
`read-write`	`read-write`





`mem`	`mem`
`mb`	`mb`








`vic`	`vic`
`0x10`	`0x10`
`8`	`8`



`int_in`	`int_in`
`0x00`	`0x00`
`8`	`8`
`read-only`	`read-only`



`irq_enable`	`irq_enable`
`0x02`	`0x02`
`8`	`8`
`read-write`	`read-write`




`irq_act`	`irq_act`
`0x06`	`0x06`
`8`	`8`
`read-only`	`read-only`



`irq_vec`	`irq_vec`
`0x08`	`0x08`
`8`	`8`
`read-only`	`read-only`




`vic`	`vic`
`mb`	`mb`

















Line 948...	Line 985...







`17`	`17`
`ext`	`ext`


`ext`	`ext`
`0x0000`	`0x0000`


`psram`	`psram`
`0x10000`	`0x10000`
`16`	`16`

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_module/] [rtl/] [xml/] [io_module_def.xml] - Diff between revs 134 and 135