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Line 25... |
// You should have received a copy of the GNU Lesser General //
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// You should have received a copy of the GNU Lesser General //
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// Public License along with this source; if not, download it //
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// Public License along with this source; if not, download it //
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// from http://www.opencores.org/lgpl.shtml //
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// from http://www.opencores.org/lgpl.shtml //
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// //
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// //
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-->
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-->
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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
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xmlns:socgen="http://opencores.org"
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xmlns:socgen="http://opencores.org"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
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xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
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http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
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http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
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opencores.org
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opencores.org
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io
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io
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io_module
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io_module
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mouse default
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mouse
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slave_clk
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slave_clk
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clk
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clk
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clk
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clk
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slave_reset
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slave_reset
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reset
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reset
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reset
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reset
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gen_registers
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102.1
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common
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none
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./tools/regtool/gen_registers
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bus_intf
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mb
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dest_dir
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../verilog
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gen_registers
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102.1
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:*common:*
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none
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tools/regtool/gen_registers
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bus_intf
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mb
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dest_dir
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../verilog
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gen_verilog
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104.0
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none
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common
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./tools/verilog/gen_verilog
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destination
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io_module_mouse
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gen_verilog
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104.0
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none
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:*common:*
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tools/verilog/gen_verilog
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destination
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io_module_mouse
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fs-common
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../verilog/top.mouse.rtl
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verilogSourcefragment
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fs-common
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../verilog/top.mouse.rtl
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verilogSourcefragment
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fs-sim
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../verilog/copyright
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verilogSourceinclude
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fs-sim
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../verilog/common/io_module_mouse
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verilogSourcemodule
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../verilog/copyright
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verilogSourceinclude
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dest_dir
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../views/sim/
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../verilog/common/io_module_mouse
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verilogSourcelibraryDir
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verilogSourcemodule
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dest_dir
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../views/sim/
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verilogSourcelibraryDir
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fs-syn
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../verilog/copyright
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verilogSourceinclude
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fs-syn
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../verilog/common/io_module_mouse
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verilogSourcemodule
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../verilog/copyright
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verilogSourceinclude
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dest_dir
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../views/syn/
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../verilog/common/io_module_mouse
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verilogSourcelibraryDir
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verilogSourcemodule
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dest_dir
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../views/syn/
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verilogSourcelibraryDir
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Hierarchical
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spirit:library="io"
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spirit:name="io_module"
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spirit:version="mouse.design"/>
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Hierarchical
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verilog
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spirit:library="Testbench"
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spirit:name="toolflow"
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spirit:version="verilog"/>
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Hierarchical
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Hierarchical
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verilog
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ipxact:library="Testbench"
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ipxact:name="toolflow"
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ipxact:version="verilog"/>
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commoncommon
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Verilog
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fs-common
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sim:*Simulation:*
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Verilog
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fs-sim
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syn:*Synthesis:*
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Verilog
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fs-syn
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common:*common:*
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Verilog
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fs-common
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doc
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sim:*Simulation:*
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Verilog
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spirit:library="Testbench"
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spirit:name="toolflow"
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fs-sim
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spirit:version="documentation"/>
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:*Documentation:*
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Verilog
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syn:*Synthesis:*
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Verilog
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fs-syn
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doc
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ipxact:library="Testbench"
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ipxact:name="toolflow"
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ipxact:version="documentation"/>
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:*Documentation:*
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Verilog
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enable
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wire
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in
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wait_n
|
clk
|
wire
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wire
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out
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in
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gpio_0_out
|
reset
|
wire
|
wire
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out
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in
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70
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gpio_0_oe
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|
wire
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out
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70
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enable
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wire
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in
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gpio_0_in
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wire
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in
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70
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gpio_1_out
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wire
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out
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70
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gpio_1_oe
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|
wire
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out
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70
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wait_n
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wire
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out
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gpio_1_in
|
gpio_0_out
|
wire
|
wire
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in
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out
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70
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70
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timer_irq
|
gpio_0_oe
|
wire
|
wire
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out
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out
|
10
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70
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pic_irq
|
|
wire
|
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out
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pic_nmi
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|
wire
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out
|
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pic_irq_in
|
gpio_0_in
|
wire
|
wire
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in
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in
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70
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70
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gpio_1_out
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|
wire
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out
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70
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cts_pad_in
|
gpio_1_oe
|
wire
|
wire
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in
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out
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70
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rts_pad_out
|
|
wire
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out
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rx_irq
|
|
wire
|
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out
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tx_irq
|
gpio_1_in
|
wire
|
wire
|
out
|
in
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70
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ps2_data_avail
|
timer_irq
|
wire
|
wire
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out
|
out
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10
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y_pos
|
pic_irq
|
wire
|
wire
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out
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out
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90
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x_pos
|
pic_nmi
|
wire
|
wire
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out
|
out
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90
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new_packet
|
pic_irq_in
|
wire
|
wire
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out
|
in
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70
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ms_mid
|
|
wire
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out
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ms_right
|
cts_pad_in
|
wire
|
wire
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out
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in
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ms_left
|
rts_pad_out
|
wire
|
wire
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out
|
out
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rx_irq
|
|
wire
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|
out
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tx_irq
|
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wire
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out
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ps2_data_avail
|
|
wire
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out
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y_pos
|
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wire
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out
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90
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x_pos
|
|
wire
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out
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90
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new_packet
|
|
wire
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out
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ms_mid
|
|
wire
|
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out
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8
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ms_right
|
mb
|
wire
|
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out
|
mb
|
|
0x00
|
|
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ms_left
|
gpio
|
wire
|
0x10
|
out
|
8
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|
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0_out
|
|
0x2
|
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8
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|
read-write
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0_oe
|
|
0x1
|
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8
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|
read-write
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0_in
|
|
0x0
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|
8
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read-only
|
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1_out
|
|
0x6
|
|
8
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read-write
|
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|
|
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|
1_oe
|
|
0x5
|
|
8
|
|
read-write
|
|
|
|
|
|
|
8
|
1_in
|
mb
|
0x4
|
|
8
|
mb
|
read-only
|
0x00
|
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|
|
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|
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|
gpio
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|
0x10
|
|
8
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|
|
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0_out
|
|
0x2
|
|
8
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|
read-write
|
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|
|
|
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|
0_oe
|
|
0x1
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|
8
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|
read-write
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|
|
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0_in
|
|
0x0
|
|
8
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|
read-only
|
|
|
|
|
|
|
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|
1_out
|
|
0x6
|
|
8
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|
read-write
|
|
|
|
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|
1_oe
|
|
0x5
|
|
8
|
|
read-write
|
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|
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1_in
|
|
0x4
|
|
8
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|
read-only
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