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// You should have received a copy of the GNU Lesser General //
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// You should have received a copy of the GNU Lesser General //
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// Public License along with this source; if not, download it //
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// Public License along with this source; if not, download it //
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// from http://www.opencores.org/lgpl.shtml //
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// from http://www.opencores.org/lgpl.shtml //
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// //
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// //
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-->
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-->
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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
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xmlns:socgen="http://opencores.org"
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xmlns:socgen="http://opencores.org"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
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xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
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http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
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http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
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opencores.org
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opencores.org
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io
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io
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io_uart
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io_uart
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def default
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def
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slave_clk
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slave_clk
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clk
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clk
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clk
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clk
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slave_reset
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slave_reset
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reset
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reset
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reset
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reset
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mb
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mb
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little
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8
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rdata
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rdata
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rdata
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rdata
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wire
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wire
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70
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70
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addr
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addr
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addr
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addr
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30
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30
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wdata
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wdata
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wdata
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wdata
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70
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70
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rd
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rd
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rd
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rd
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wr
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wr
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wr
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wr
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cs
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cs
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cs
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cs
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little
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8
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gen_registers
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102.1
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common
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none
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./tools/regtool/gen_registers
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bus_intf
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mb
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dest_dir
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../verilog
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gen_verilog
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104.0
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none
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common
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./tools/verilog/gen_verilog
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destination
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io_uart_def
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gen_registers
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102.1
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:*common:*
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none
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tools/regtool/gen_registers
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bus_intf
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mb
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dest_dir
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../verilog
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gen_verilog
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104.0
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none
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:*common:*
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tools/verilog/gen_verilog
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destination
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io_uart_def
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fs-common
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../verilog/top.body
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verilogSourcefragment
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fs-sim
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fs-common
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../verilog/copyright.v
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../verilog/top.body
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verilogSourceinclude
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verilogSourcefragment
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fs-sim
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../verilog/common/io_uart_def
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verilogSourcemodule
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mb
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../verilog/io_uart_def_mb
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../verilog/copyright.v
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verilogSourcemodule
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verilogSourceinclude
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../verilog/common/io_uart_def
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verilogSourcemodule
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mb
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../verilog/io_uart_def_mb
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verilogSourcemodule
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Hierarchical
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spirit:library="io"
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spirit:name="io_uart"
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spirit:version="def.design"/>
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verilog
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spirit:library="Testbench"
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spirit:name="toolflow"
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spirit:version="verilog"/>
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Hierarchical
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commoncommon
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Verilog
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fs-common
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sim:*Simulation:*
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Hierarchical
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Verilog
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Hierarchical
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fs-sim
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syn:*Synthesis:*
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verilog
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Verilog
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ipxact:library="Testbench"
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fs-sim
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ipxact:name="toolflow"
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ipxact:version="verilog"/>
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doc
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spirit:library="Testbench"
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spirit:name="toolflow"
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spirit:version="documentation"/>
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:*Documentation:*
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Verilog
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common:*common:*
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Verilog
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fs-common
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sim:*Simulation:*
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Verilog
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fs-sim
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syn:*Synthesis:*
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Verilog
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fs-sim
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doc
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ipxact:library="Testbench"
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ipxact:name="toolflow"
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ipxact:version="documentation"/>
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:*Documentation:*
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Verilog
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PRESCALE5'b01100
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PRE_SIZE5
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DIV0
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enable
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wire
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in
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cts_pad_in
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wire
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in
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rts_pad_out
|
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wire
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out
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rx_irq
|
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reg
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out
|
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tx_irq
|
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reg
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out
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enable
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wire
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in
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clk
|
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wire
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in
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reset
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wire
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in
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cs
|
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wire
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in
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mb
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8
|
|
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mb
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0x00
|
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rd
|
mb_microbus
|
wire
|
0x10
|
in
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8
|
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wr
|
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wire
|
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in
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xmit_data
|
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0x0
|
|
8
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write-only
|
|
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|
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addr
|
rcv_data
|
wire
|
0x2
|
in
|
8
|
30
|
read-only
|
|
|
|
|
|
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|
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wdata
|
cntrl
|
wire
|
0x4
|
in
|
8
|
70
|
read-write
|
|
|
|
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|
|
|
status
|
|
0x6
|
|
8
|
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read-only
|
|
|
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|
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rdata
|
|
wire
|
|
out
|
|
70
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|
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cts_pad_in
|
|
wire
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in
|
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rts_pad_out
|
|
wire
|
|
out
|
|
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rx_irq
|
|
reg
|
|
out
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tx_irq
|
|
reg
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|
out
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mb
|
|
8
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|
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mb
|
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0x00
|
|
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mb_microbus
|
|
0x10
|
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8
|
|
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xmit_data
|
|
0x0
|
|
8
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write-only
|
|
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rcv_data
|
|
0x2
|
|
8
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|
read-only
|
|
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cntrl
|
|
0x4
|
|
8
|
|
read-write
|
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status
|
|
0x6
|
|
8
|
|
read-only
|
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