URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [flash_memcontrl/] [sim/] [testbenches/] [xml/] [flash_memcontrl_def_duth.design.xml] - Diff between revs 133 and 135

-Rev 133
+Rev 135
 Line 4...
 // Generated File Do Not EDIT                                                                         //
 //                                                                                                    //
 // ./tools/verilog/gen_tb -vendor opencores.org -library logic  -component flash_memcontrl  -version def //
 //                                                                                                    //
 -->
-xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
+xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
 xmlns:socgen="http://opencores.org"
 xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
-xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
+xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
-http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
+http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 opencores.org
 logic
 flash_memcontrl
 def_duth.design
 addr
 clk
 cs
 flashcs_n_out
 flashrp_n_out
 flashststs_in
 lb
 memadr_out
 memdb_in
 memdb_oe
 memdb_out
 memoe_n_out
 memwr_n_out
 ramadv_n_out
 ramclk_out
 ramcre_out
 ramcs_n_out
 ramlb_n_out
 ramub_n_out
 ramwait_in
 rd
 rdata
 reset
 stb
 ub
 wait_out
 wdata
 wr
 dut
  ADDR_BITS