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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [micro_bus/] [rtl/] [xml/] [micro_bus_def.xml] - Diff between revs 134 and 135

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Rev 134	Rev 135
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`// You should have received a copy of the GNU Lesser General //`	`// You should have received a copy of the GNU Lesser General //`
`// Public License along with this source; if not, download it //`	`// Public License along with this source; if not, download it //`
`// from http://www.opencores.org/lgpl.shtml //`	`// from http://www.opencores.org/lgpl.shtml //`
`// //`	`// //`
`-->`	`-->`

`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`	`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
`xmlns:socgen="http://opencores.org"`	`xmlns:socgen="http://opencores.org"`
`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`	`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`	`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`

`opencores.org`	`opencores.org`
`logic`	`logic`
`micro_bus`	`micro_bus`
`def default`	`def`





`slave_clk`	`slave_clk`





`clk`
`clk`






	`clk`
	`clk`



`slave_reset`





`reset`
`reset`







`master_enable`





`enable`
`enable`





`cpu`













`addr`
`addr_in`
`150`



`rdata`
`rdata_out`
`reg`
`150`




	`slave_reset`






`wdata`
`wdata_in`	`reset`
`70`	`reset`







`wr`
`wr_in`






`rd`
`rd_in`



	`master_enable`











	`enable`
	`enable`








`mem`	`cpu`










	`addr`
	`addr_in`
	`150`



	`rdata`
	`rdata_out`
	`reg`
	`150`




`addr`
`mem_addr`
`150`




`cs`
`mem_cs`
`reg`




`wdata`	`wdata`
`mem_wdata`	`wdata_in`
`150`	`70`




`rdata`
`mem_rdata`
`150`




	`wr`
	`wr_in`




`wait`
`mem_wait`
`10`




	`rd`
	`rd_in`




`rd`
`mem_rd`




`wr`
`mem_wr`




















`data`








`addr`
`data_addr`
`111`



	`mem`
`cs`
`data_cs`
`reg`




`wdata`
`data_wdata`
`150`




`rdata`	`addr`
`data_rdata`	`mem_addr`
`150`	`150`




	`cs`
	`mem_cs`
	`reg`




`be`	`wdata`
`data_be`	`mem_wdata`
`10`	`150`




	`rdata`
	`mem_rdata`
	`150`




`rd`
`data_rd`




`wr`	`wait`
`data_wr`	`mem_wait`
	`10`







	`rd`
	`mem_rd`




	`wr`
	`mem_wr`





`io_reg`








`addr`
`io_reg_addr`
`70`




`cs`
`io_reg_cs`
`reg`




`wdata`
`io_reg_wdata`
`70`




`rdata`
`io_reg_rdata`
`150`





`wait`
`io_reg_wait`





`rd`
`io_reg_rd`



	`data`
`wr`
`io_reg_wr`







	`addr`
	`data_addr`
	`111`




	`cs`
	`data_cs`
	`reg`




	`wdata`
	`data_wdata`
	`150`



`ext_mem`
	`rdata`
	`data_rdata`
	`150`






	`be`
	`data_be`
	`10`






`addr`	`rd`
`ext_mem_addr`	`data_rd`
`130`




`cs`	`wr`
`ext_mem_cs`	`data_wr`
`reg`




`wdata`
`ext_mem_wdata`
`150`




`rdata`
`ext_mem_rdata`
`150`





`wait`
`ext_mem_wait`





`rd`
`ext_mem_rd`




`wr`
`ext_mem_wr`









	`io_reg`







`prog_rom_mem`
	`addr`
	`io_reg_addr`
	`70`




	`cs`
	`io_reg_cs`
	`reg`




	`wdata`
	`io_reg_wdata`
	`70`




`addr`	`rdata`
`prog_rom_mem_addr`	`io_reg_rdata`
`110`	`150`




`cs`
`prog_rom_mem_cs`
`reg`




`wdata`	`wait`
`prog_rom_mem_wdata`	`io_reg_wait`
`150`




`rdata`
`prog_rom_mem_rdata`
`150`




	`rd`
	`io_reg_rd`




`rd`	`wr`
`prog_rom_mem_rd`	`io_reg_wr`




`wr`
`prog_rom_mem_wr`











`sh_prog_rom_mem`






`addr`
`sh_prog_rom_mem_addr`
`110`




`cs`
`sh_prog_rom_mem_cs`
`reg`




`wdata`
`sh_prog_rom_mem_wdata`
`150`



	`ext_mem`
`rdata`
`sh_prog_rom_mem_rdata`
`150`






`rd`	`addr`
`sh_prog_rom_mem_rd`	`ext_mem_addr`
	`130`




`wr`	`cs`
`sh_prog_rom_mem_wr`	`ext_mem_cs`
	`reg`




	`wdata`
	`ext_mem_wdata`
	`150`




	`rdata`
	`ext_mem_rdata`
	`150`





	`wait`
	`ext_mem_wait`






	`rd`
	`ext_mem_rd`




	`wr`
	`ext_mem_wr`










`gen_verilog`
`104.0`
`none`
`common`
`./tools/verilog/gen_verilog`


`destination`
`micro_bus_def`















`fs-common`

	`prog_rom_mem`

`../verilog/top.body`
`verilogSourcefragment`




	`addr`
	`prog_rom_mem_addr`
	`110`




	`cs`
	`prog_rom_mem_cs`
	`reg`




`fs-sim`	`wdata`
	`prog_rom_mem_wdata`
	`150`




	`rdata`
`../verilog/copyright.v`	`prog_rom_mem_rdata`
`verilogSourceinclude`	`150`





`../verilog/common/micro_bus_def`
`verilogSourcemodule`



	`rd`
	`prog_rom_mem_rd`




	`wr`
	`prog_rom_mem_wr`






`fs-syn`



`../verilog/copyright.v`
`verilogSourceinclude`




`../verilog/common/micro_bus_def`
`verilogSourcemodule`













	`sh_prog_rom_mem`










	`addr`
	`sh_prog_rom_mem_addr`
	`110`




	`cs`
	`sh_prog_rom_mem_cs`
	`reg`




	`wdata`
	`sh_prog_rom_mem_wdata`
	`150`




`verilog`	`rdata`
	`sh_prog_rom_mem_rdata`
	`150`
`spirit:library="Testbench"`
`spirit:name="toolflow"`
`spirit:version="verilog"/>`





	`rd`
	`sh_prog_rom_mem_rd`




	`wr`
	`sh_prog_rom_mem_wr`









`commoncommon`

`Verilog`


`fs-common`






`sim:Simulation:`

`Verilog`


`fs-sim`




`syn:Synthesis:`

`Verilog`


`fs-syn`





`doc`


`spirit:library="Testbench"`
`spirit:name="toolflow"`
`spirit:version="documentation"/>`

`:Documentation:`
`Verilog`








	`gen_verilog`
	`104.0`
	`none`
	`:common:`
	`tools/verilog/gen_verilog`


	`destination`
	`micro_bus_def`














	`fs-common`



	`../verilog/top.body`
	`verilogSourcefragment`






	`fs-sim`



	`../verilog/copyright.v`
	`verilogSourceinclude`




	`../verilog/common/micro_bus_def`
	`verilogSourcemodule`




`cpu`


`io_reg`
`0x8000`



	`fs-syn`


`data`
`0x1000`	`../verilog/copyright.v`
	`verilogSourceinclude`



`ext_mem`
`0x4000`	`../verilog/common/micro_bus_def`
	`verilogSourcemodule`




`prog_rom_mem`
`0xc000`




`sh_prog_rom_mem`
`0xf000`















`io_reg`
`0x8000`
`8`





`data`
`0x1000`
`8`



	`verilog`


	`ipxact:library="Testbench"`
	`ipxact:name="toolflow"`
	`ipxact:version="verilog"/>`





`mem`
`0x0000`
`8`






`ext_mem`	`common:common:`
`0x4000`
`8`


	`Verilog`


	`fs-common`




`prog_rom_mem`
`0xff00`
`8`



	`sim:Simulation:`

	`Verilog`
`sh_prog_rom_mem`
`0xc000`
`8`	`fs-sim`




	`syn:Synthesis:`

	`Verilog`


	`fs-syn`






	`doc`


	`ipxact:library="Testbench"`
	`ipxact:name="toolflow"`
	`ipxact:version="documentation"/>`

	`:Documentation:`
	`Verilog`

























	`cpu`


	`io_reg`
	`0x8000`




	`data`
	`0x1000`



	`ext_mem`
	`0x4000`




	`prog_rom_mem`
	`0xc000`




	`sh_prog_rom_mem`
	`0xf000`














	`io_reg`
	`0x8000`
	`8`




	`data`
	`0x1000`
	`8`





	`mem`
	`0x0000`
	`8`






	`ext_mem`
	`0x4000`
	`8`




	`prog_rom_mem`
	`0xff00`
	`8`




	`sh_prog_rom_mem`
	`0xc000`
	`8`

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [micro_bus/] [rtl/] [xml/] [micro_bus_def.xml] - Diff between revs 134 and 135