Line 25... |
Line 25... |
// You should have received a copy of the GNU Lesser General //
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// You should have received a copy of the GNU Lesser General //
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// Public License along with this source; if not, download it //
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// Public License along with this source; if not, download it //
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// from http://www.opencores.org/lgpl.shtml //
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// from http://www.opencores.org/lgpl.shtml //
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// //
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// //
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-->
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-->
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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
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xmlns:socgen="http://opencores.org"
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xmlns:socgen="http://opencores.org"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
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xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
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http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
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http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
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opencores.org
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opencores.org
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logic
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logic
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micro_bus
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micro_bus
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def default
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def
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slave_clk
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slave_clk
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clk
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clk
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clk
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clk
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slave_reset
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reset
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reset
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master_enable
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enable
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enable
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cpu
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addr
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addr_in
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150
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rdata
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rdata_out
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reg
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150
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slave_reset
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wdata
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wdata_in
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reset
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70
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reset
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wr
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wr_in
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rd
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rd_in
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master_enable
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enable
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enable
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mem
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cpu
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addr
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addr_in
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150
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rdata
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rdata_out
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reg
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150
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addr
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mem_addr
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150
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cs
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mem_cs
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reg
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wdata
|
wdata
|
mem_wdata
|
wdata_in
|
150
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70
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rdata
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mem_rdata
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150
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wr
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wr_in
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wait
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mem_wait
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10
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rd
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rd_in
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rd
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mem_rd
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wr
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mem_wr
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data
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addr
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data_addr
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111
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mem
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cs
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data_cs
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reg
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wdata
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data_wdata
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150
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rdata
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addr
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data_rdata
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mem_addr
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150
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150
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cs
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mem_cs
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reg
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be
|
wdata
|
data_be
|
mem_wdata
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10
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150
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rdata
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mem_rdata
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150
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rd
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data_rd
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wr
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wait
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data_wr
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mem_wait
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10
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rd
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mem_rd
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wr
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mem_wr
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io_reg
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addr
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io_reg_addr
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70
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cs
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io_reg_cs
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reg
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wdata
|
|
io_reg_wdata
|
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70
|
|
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rdata
|
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io_reg_rdata
|
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150
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wait
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io_reg_wait
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rd
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io_reg_rd
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data
|
wr
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io_reg_wr
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addr
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data_addr
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111
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cs
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data_cs
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reg
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wdata
|
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data_wdata
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150
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ext_mem
|
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rdata
|
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data_rdata
|
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150
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be
|
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data_be
|
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10
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addr
|
rd
|
ext_mem_addr
|
data_rd
|
130
|
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cs
|
wr
|
ext_mem_cs
|
data_wr
|
reg
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wdata
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ext_mem_wdata
|
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150
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rdata
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ext_mem_rdata
|
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150
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wait
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ext_mem_wait
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rd
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ext_mem_rd
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wr
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ext_mem_wr
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io_reg
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prog_rom_mem
|
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addr
|
|
io_reg_addr
|
|
70
|
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cs
|
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io_reg_cs
|
|
reg
|
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wdata
|
|
io_reg_wdata
|
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70
|
|
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addr
|
rdata
|
prog_rom_mem_addr
|
io_reg_rdata
|
110
|
150
|
|
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cs
|
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prog_rom_mem_cs
|
|
reg
|
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|
wdata
|
wait
|
prog_rom_mem_wdata
|
io_reg_wait
|
150
|
|
|
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rdata
|
|
prog_rom_mem_rdata
|
|
150
|
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rd
|
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io_reg_rd
|
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rd
|
wr
|
prog_rom_mem_rd
|
io_reg_wr
|
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wr
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prog_rom_mem_wr
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sh_prog_rom_mem
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addr
|
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sh_prog_rom_mem_addr
|
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110
|
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cs
|
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sh_prog_rom_mem_cs
|
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reg
|
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wdata
|
|
sh_prog_rom_mem_wdata
|
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150
|
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ext_mem
|
rdata
|
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sh_prog_rom_mem_rdata
|
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150
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rd
|
addr
|
sh_prog_rom_mem_rd
|
ext_mem_addr
|
|
130
|
|
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|
|
|
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|
wr
|
cs
|
sh_prog_rom_mem_wr
|
ext_mem_cs
|
|
reg
|
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|
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|
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|
wdata
|
|
ext_mem_wdata
|
|
150
|
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|
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rdata
|
|
ext_mem_rdata
|
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150
|
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wait
|
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ext_mem_wait
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rd
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ext_mem_rd
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wr
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ext_mem_wr
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|
gen_verilog
|
|
104.0
|
|
none
|
|
common
|
|
./tools/verilog/gen_verilog
|
|
|
|
|
|
destination
|
|
micro_bus_def
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fs-common
|
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prog_rom_mem
|
|
|
../verilog/top.body
|
|
verilogSourcefragment
|
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addr
|
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prog_rom_mem_addr
|
|
110
|
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|
cs
|
|
prog_rom_mem_cs
|
|
reg
|
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fs-sim
|
wdata
|
|
prog_rom_mem_wdata
|
|
150
|
|
|
|
|
|
|
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|
|
rdata
|
../verilog/copyright.v
|
prog_rom_mem_rdata
|
verilogSourceinclude
|
150
|
|
|
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|
../verilog/common/micro_bus_def
|
|
verilogSourcemodule
|
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rd
|
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prog_rom_mem_rd
|
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wr
|
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prog_rom_mem_wr
|
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|
fs-syn
|
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|
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|
|
|
../verilog/copyright.v
|
|
verilogSourceinclude
|
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|
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|
../verilog/common/micro_bus_def
|
|
verilogSourcemodule
|
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sh_prog_rom_mem
|
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|
addr
|
|
sh_prog_rom_mem_addr
|
|
110
|
|
|
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|
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|
cs
|
|
sh_prog_rom_mem_cs
|
|
reg
|
|
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|
wdata
|
|
sh_prog_rom_mem_wdata
|
|
150
|
|
|
|
|
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|
|
verilog
|
rdata
|
|
sh_prog_rom_mem_rdata
|
|
150
|
spirit:library="Testbench"
|
|
spirit:name="toolflow"
|
|
spirit:version="verilog"/>
|
|
|
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|
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|
rd
|
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sh_prog_rom_mem_rd
|
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|
wr
|
|
sh_prog_rom_mem_wr
|
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|
commoncommon
|
|
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|
Verilog
|
|
|
|
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|
fs-common
|
|
|
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|
sim:*Simulation:*
|
|
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|
Verilog
|
|
|
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fs-sim
|
|
|
|
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|
|
syn:*Synthesis:*
|
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|
Verilog
|
|
|
|
|
|
fs-syn
|
|
|
|
|
|
|
|
|
|
|
|
doc
|
|
|
|
|
|
spirit:library="Testbench"
|
|
spirit:name="toolflow"
|
|
spirit:version="documentation"/>
|
|
|
|
:*Documentation:*
|
|
Verilog
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
gen_verilog
|
|
104.0
|
|
none
|
|
:*common:*
|
|
tools/verilog/gen_verilog
|
|
|
|
|
|
destination
|
|
micro_bus_def
|
|
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|
fs-common
|
|
|
|
|
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|
|
../verilog/top.body
|
|
verilogSourcefragment
|
|
|
|
|
|
|
|
|
|
|
|
|
|
fs-sim
|
|
|
|
|
|
|
|
../verilog/copyright.v
|
|
verilogSourceinclude
|
|
|
|
|
|
|
|
|
|
../verilog/common/micro_bus_def
|
|
verilogSourcemodule
|
|
|
|
|
|
|
|
|
cpu
|
|
|
|
|
|
io_reg
|
|
0x8000
|
|
|
|
|
|
|
|
|
fs-syn
|
|
|
|
|
data
|
|
0x1000
|
../verilog/copyright.v
|
|
verilogSourceinclude
|
|
|
|
|
|
|
ext_mem
|
|
0x4000
|
../verilog/common/micro_bus_def
|
|
verilogSourcemodule
|
|
|
|
|
|
|
|
|
prog_rom_mem
|
|
0xc000
|
|
|
|
|
|
|
|
|
|
sh_prog_rom_mem
|
|
0xf000
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
io_reg
|
|
0x8000
|
|
8
|
|
|
|
|
|
|
|
|
|
|
|
data
|
|
0x1000
|
|
8
|
|
|
|
|
|
|
|
|
verilog
|
|
|
|
|
|
ipxact:library="Testbench"
|
|
ipxact:name="toolflow"
|
|
ipxact:version="verilog"/>
|
|
|
|
|
|
|
|
|
|
|
mem
|
|
0x0000
|
|
8
|
|
|
|
|
|
|
|
|
|
|
|
|
|
ext_mem
|
common:*common:*
|
0x4000
|
|
8
|
|
|
|
|
|
|
Verilog
|
|
|
|
|
|
fs-common
|
|
|
|
|
|
|
|
|
prog_rom_mem
|
|
0xff00
|
|
8
|
|
|
|
|
|
|
|
|
sim:*Simulation:*
|
|
|
|
Verilog
|
sh_prog_rom_mem
|
|
0xc000
|
|
8
|
fs-sim
|
|
|
|
|
|
|
|
|
|
syn:*Synthesis:*
|
|
|
|
Verilog
|
|
|
|
|
|
fs-syn
|
|
|
|
|
|
|
|
|
|
|
|
|
|
doc
|
|
|
|
|
|
ipxact:library="Testbench"
|
|
ipxact:name="toolflow"
|
|
ipxact:version="documentation"/>
|
|
|
|
:*Documentation:*
|
|
Verilog
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
cpu
|
|
|
|
|
|
io_reg
|
|
0x8000
|
|
|
|
|
|
|
|
|
|
data
|
|
0x1000
|
|
|
|
|
|
|
|
ext_mem
|
|
0x4000
|
|
|
|
|
|
|
|
|
|
prog_rom_mem
|
|
0xc000
|
|
|
|
|
|
|
|
|
|
sh_prog_rom_mem
|
|
0xf000
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
io_reg
|
|
0x8000
|
|
8
|
|
|
|
|
|
|
|
|
|
data
|
|
0x1000
|
|
8
|
|
|
|
|
|
|
|
|
|
|
|
mem
|
|
0x0000
|
|
8
|
|
|
|
|
|
|
|
|
|
|
|
|
|
ext_mem
|
|
0x4000
|
|
8
|
|
|
|
|
|
|
|
|
|
prog_rom_mem
|
|
0xff00
|
|
8
|
|
|
|
|
|
|
|
|
|
sh_prog_rom_mem
|
|
0xc000
|
|
8
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|